infrastructure_top.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module infrastructure_top 
    (
       //inputs
             reset_in,
//NO_DCM	 clk_int,
//NO_DCM	 clk90_int,         
             sys_clk_ibuf,     
//NO_DCM     dcm_lock,
       //outputs        
       delay_sel_val1_val_tb,  
       delay_sel_val1_val_rl,  
       sys_rst_val,          
       sys_rst90_val,        
//YES_DCM  clk_int_val,          
//YES_DCM  clk90_int_val,
           sys_rst180_val,       
           sys_rst270_val,
	     wait_200us
    );
//Input/Output declarations  
input         reset_in;         
//NO_DCM input         clk_int;
//NO_DCM input         clk90_int;
//NO_DCM input         dcm_lock;
         input         sys_clk_ibuf;     
output [4:0] delay_sel_val1_val_tb;  
output [4:0] delay_sel_val1_val_rl;  
output       sys_rst_val;          
output       sys_rst90_val;        
output       sys_rst180_val;       
output       sys_rst270_val;
output       wait_200us;       
//YES_DCM output       clk_int_val;          
//YES_DCM output       clk90_int_val;        

wire user_rst;
//YES_DCM wire clk_int; 
//YES_DCM wire clk90_int;
//YES_DCM wire dcm_lock; 

reg sys_rst_o;              
reg sys_rst_1;              
reg sys_rst;                
reg sys_rst90_o;            
reg sys_rst90_1;            
reg sys_rst90;              
reg sys_rst180_o;           
reg sys_rst180_1;           
reg sys_rst180;             
reg sys_rst270_o;          
reg sys_rst270_1;          
reg sys_rst270;            

wire stuck_at1;  
wire vcc;

wire clk_int_val1;
wire clk_int_val2;
wire clk90_int_val1;
wire clk90_int_val2;
//wire [4:0] delay_sel_val;
wire [4:0] delay_sel_val_tb;
wire [4:0] delay_sel_val_rl;

//200us reg
reg [15:0] Counter200;
reg      wait_200us;//added
reg      wait_clk90;//added



//YES_DCM assign clk_int_val = clk_int;
//YES_DCM assign clk90_int_val = clk90_int;


assign sys_rst_val = sys_rst;
assign sys_rst90_val = sys_rst90;
assign sys_rst180_val = sys_rst180;
assign sys_rst270_val = sys_rst270;

//assign delay_sel_val1_val = delay_sel_val;

assign delay_sel_val1_val_tb = delay_sel_val_tb;
assign delay_sel_val1_val_rl = delay_sel_val_rl;


//-----   To remove delta delays in the clock signals observed during simulation ,Following signals are used 

assign clk_int_val1 = clk_int;
assign clk90_int_val1 = clk90_int;
assign clk_int_val2 = clk_int_val1;
assign clk90_int_val2 = clk90_int_val1;
assign vcc       = 1'b1;
assign user_rst  = ~ reset_in;                                        

//assign delay_sel_val1 = (rst_calib1 == 1'b0 && rst_calib1_r2 == 1'b0) ? delay_sel_val :delay_sel_val1_r;

//For 200us during power up
always @(posedge clk_int_val2)
begin
   if(user_rst == 1'b1 || dcm_lock == 1'b0)
   begin
     wait_200us <= 1'b1;
     Counter200     <= 16'b0;
   end 
   else
   begin  
      if( Counter200[15] & Counter200[13] & wait_200us)//(THIS IS DIFFERENT IN DDR2)
         wait_200us <=1'b0;
      else if (wait_200us)
         Counter200 <= Counter200 + 1;
      else    
         Counter200 <= Counter200;
   end 
end


always @(posedge clk90_int_val2)
begin
   if(user_rst == 1'b1 || dcm_lock == 1'b0)
      wait_clk90 <= 1'b1;
   else
      wait_clk90 <= wait_200us;
end



always@(posedge clk_int_val2)
begin
    if(user_rst == 1'b1 || dcm_lock == 1'b0 || wait_200us == 1'b1 )
      begin
      sys_rst_o <= 1'b1;
      sys_rst_1 <= 1'b1;
      sys_rst   <= 1'b1;
      end  
   else
      begin
      sys_rst_o <= 1'b0;
      sys_rst_1 <= sys_rst_o;
      sys_rst   <= sys_rst_1;
      end
end      


always@(posedge clk90_int_val2)
begin
  if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_clk90 == 1'b1)
      begin
      sys_rst90_o <= 1'b1;
      sys_rst90_1 <= 1'b1;
      sys_rst90   <= 1'b1;
      end
  else
      begin
      sys_rst90_o <= 1'b0;
      sys_rst90_1 <= sys_rst90_o;
      sys_rst90   <= sys_rst90_1;
      end
end


always@(negedge clk_int_val2)
begin
  if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_200us == 1'b1)
      begin 
      sys_rst180_o <= 1'b1;
      sys_rst180_1 <= 1'b1;
      sys_rst180   <= 1'b1;
      end
  else
      begin
      sys_rst180_o <= 1'b0;
      sys_rst180_1 <= sys_rst180_o;
      sys_rst180   <= sys_rst180_1;
      end
end      


always@(negedge clk90_int_val2)
begin
  if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_clk90 == 1'b1)
      begin
      sys_rst270_o <= 1'b1;
      sys_rst270_1 <= 1'b1;
      sys_rst270   <= 1'b1;
      end
  else
      begin
      sys_rst270_o <= 1'b0;
      sys_rst270_1 <= sys_rst270_o;
      sys_rst270   <= sys_rst270_1;
      end

end 
///----  Component instantiations  ----

                                   
//YES_DCM  clk_dcm clk_dcm0  (
//YES_DCM                              .input_clk   ( sys_clk_ibuf),
//YES_DCM                              .rst         ( user_rst),                            
//YES_DCM                              .clk         ( clk_int),
//YES_DCM                              .clk90       ( clk90_int),
//YES_DCM                              .dcm_lock    ( dcm_lock)
//YES_DCM                             ); 
                            
 cal_top cal_top0 (                                                 
                             
                             .clk        ( clk_int_val2),          
                             .clk0dcmlock ( dcm_lock),  
                             .reset       ( reset_in),      
                             .okToSelTap  ( vcc),
//                             .tapForDqs   ( delay_sel_val)
                             .tapForDqs_tb   ( delay_sel_val_tb),
                             .tapForDqs_rl   ( delay_sel_val_rl)


                             );       
                                          
endmodule