cal_top.v

XILINX memory interface generator. XILINX的外部存储器接口。

///**********************************************************************************
 //* Top level for calibration circuit.
 //*  - instantiate DCM, calib control, and ckt to calibrate
//*********************************************************************************/

`timescale 1ns/100ps

`define noMuxF5 1'b1


module cal_top(
			clk,
			clk0dcmlock,
			reset,
			okToSelTap,
			tapForDqs_tb,
			tapForDqs_rl);

// Ports
               
   input            clk;
   input 	  	  clk0dcmlock;
   input 	  	  reset;
   input 	  	  okToSelTap;
   
//   output 	[4:0]   tapForDqs;
   output 	[4:0]   tapForDqs_tb;
   output 	[4:0]   tapForDqs_rl;
   
// Data Types
   wire     [31:0]  flop2;
   wire             okToSelTap; 	 
   wire 	  	  reset;
   wire 	[4:0]   selTap;
//   wire 	[4:0]   tapForDqs;
   wire 	[4:0]   tapForDqs_tb;
   wire 	[4:0]   tapForDqs_rl;

   wire 	[3:0]   state;
   


// Internal Signals

   reg 	  fpga_rst;//
   

always @ (posedge clk)
	begin
  	  	 #1 fpga_rst <= ~(reset & clk0dcmlock);
	end

//*********************************** New Calibration Module **************************************/ 
//************ To Calculate The Number Of Lut Delays To Be Inserted in Dqs Path *******************/ 
//	
//	cal_ctl cal_ctl0(
//					 .flop2 (flop2),
//					 .clk (clk) ,
//					 .reset (fpga_rst),
//					 .okToSelTap (okToSelTap),
//					 .tapForDqs (tapForDqs[4:0])
//									);
cal_ctl cal_ctl0(
					 .flop2 (flop2),
					 .clk (clk) ,
					 .reset (fpga_rst),
					 .okToSelTap (okToSelTap),
					 .tapForDqs_tb (tapForDqs_tb),
					 .tapForDqs_rl (tapForDqs_rl)
									);
				
//********************************* Tape Delay Circuit *********************************************/ 
//*** To Find How Many Inverters It Takes For Transition Because of change in PVT Conditions ******/

	tap_dly tap_dly0(
		   .clk (clk),
		   .reset (fpga_rst),
		   .tapIn (clk),
		   .flop2 (flop2)
		  );
   

  
endmodule // cal_top