fifo_0_wr_en.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 41 行

//  fifo_wr_en is derived  by ORing -
//  "rst_dqs_div" , delayed rst_dqs_div with negedge of the ddr_dqs 

  `timescale 1ns/100ps
module fifo_0_wr_en (
			clk,
			reset,
			din,
			rst_dqs_delay_n,
			dout
		   );
		   
input clk;
input reset;
input din;
output rst_dqs_delay_n;
output dout;


wire	din_delay	;
wire  TIE_HIGH;
 

assign	rst_dqs_delay_n = ~ din_delay;
assign	dout = din || din_delay;

	
assign TIE_HIGH = 1'b1;


 FDCE delay_ff   (
                      .Q(din_delay),
                      .C(clk),
                      .CE(TIE_HIGH),
                      .CLR(reset),
                      .D(din)
                     );

endmodule