data_path_rst.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 72 行

  `timescale 1ns/100ps
module data_path_rst (

     clk,       
     clk90,
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,     
     reset,     
     reset90,   
     reset180,  
     reset270,  
     reset_r,   
     reset90_r, 
     reset180_r,
     reset270_r
     );

input     clk;        
input     clk90;   
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;   
input     reset;      
input     reset90;    
input     reset180;   
input     reset270;   
output     reset_r;   
output     reset90_r; 
output     reset180_r;
output     reset270_r;


//SYN_REMOVECOMMENT wire clk180 /* synthesis syn_keep=1 */;
//SYN_REMOVECOMMENT wire clk270 /* synthesis syn_keep=1 */;   


  
// ********************************
//  generation of clk180 and clk270
// *********************************


//SYN_REMOVECOMMENT assign  clk180 = ~ clk;
//SYN_REMOVECOMMENT assign  clk270 = ~ clk90;



FD rst0_r  (                      
             .Q(reset_r),
             .C(clk),
             .D(reset)
             );

FD rst90_r  (                      
              .Q(reset90_r),
              .C(clk90),
              .D(reset90)
              );

FD rst180_r (                      
              .Q(reset180_r),
              .C(clk180),
              .D(reset180)
             );                                            

FD rst270_r (                      
              .Q(reset270_r),
              .C(clk270),
              .D(reset270)
             );                                            
                  
                  
endmodule