fifo_1_wr_en.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 44 行

//  fifo_wr_en is derived  by ORing -
//  "rst_dqs_div" , delayed rst_dqs_div with negedge of the ddr_dqs 

  `timescale 1ns/100ps
module fifo_1_wr_en (
			clk,
			rst_dqs_delay_n,
 	   		reset,
			din,
		        dout
	  	);

input clk;
input rst_dqs_delay_n;
input reset;
input din;
output dout;

wire	din_delay_1;
wire TIE_HIGH;
wire dout0;
wire rst_dqs_delay;


	
assign 	rst_dqs_delay = ~ rst_dqs_delay_n;	
assign	dout0 = din & rst_dqs_delay_n;
assign	dout = rst_dqs_delay | din_delay_1;
assign TIE_HIGH =1'b1;


FDCE delay_ff_1   (
                      .Q(din_delay_1),
                      .C(clk),
                      .CE(TIE_HIGH),
                      .CLR(reset),
                      .D(dout0)
                     );



endmodule