cal_ctl.v

XILINX memory interface generator. XILINX的外部存储器接口。

         end
      end 
	else if ((cnt[4:0] == 5'd15) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[15] ~^ tap_dly_reg[16]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin			    
               trans_twoDtct <= 1'b1;
		end
		else
		begin	    
		   trans_oneDtct <= 1'b1;
		end
         end 
         else 
	   begin                
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd16) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[16] ~^ tap_dly_reg[17]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin			    
               trans_twoDtct <= 1'b1;
	      end
	      else
		begin		  
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin                
            trans_oneDtct <= trans_oneDtct;    
	      trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd17) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[17] ~^ tap_dly_reg[18]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin			    
               trans_twoDtct <= 1'b1;
		end
		else
		begin		    
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin                
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd18) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[18] ~^ tap_dly_reg[19]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin		    
               trans_twoDtct <= 1'b1;
	      end
		else
		begin
		   trans_oneDtct <= 1'b1;
	      end
         end 
	   else 
	   begin                
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd19) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[19] ~^ tap_dly_reg[20]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin		  
               trans_twoDtct <= 1'b1;
	      end
	      else
		begin		  
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin               
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd20) & (trans_twoDtct == 1'b0)) 
      begin
         if (tap_dly_reg[20] ~^ tap_dly_reg[21]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
	      begin		 
               trans_twoDtct <= 1'b1;
		end
		else
		begin		 
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin             
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd21) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[21] ~^ tap_dly_reg[22]) 
	   begin
            if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin		 
               trans_twoDtct <= 1'b1;
		end
		else
		begin		 
		   trans_oneDtct <= 1'b1;
	      end
         end 
	   else 
	   begin             
            trans_oneDtct <= trans_oneDtct;    
	      trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd22) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[22] ~^ tap_dly_reg[23]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin			 
               trans_twoDtct <= 1'b1;
		end
		else
		begin		 
		   trans_oneDtct <= 1'b1;
	      end
         end 
	   else 
	   begin             
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd23) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[23] ~^ tap_dly_reg[24]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin			
               trans_twoDtct <= 1'b1;
		end
	      else
		begin
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
      else if ((cnt[4:0] == 5'd24) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[24] ~^ tap_dly_reg[25]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin			
               trans_twoDtct <= 1'b1;
	      end
		else
		begin		 
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin             
            trans_oneDtct <= trans_oneDtct;    
	      trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd25) & (trans_twoDtct == 1'b0))
	begin
         if (tap_dly_reg[25] ~^ tap_dly_reg[26]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin			 
               trans_twoDtct <= 1'b1;
	      end
	      else
	      begin		 
               trans_oneDtct <= 1'b1;
	      end
         end 
	   else 
	   begin            
            trans_oneDtct <= trans_oneDtct;    
	      trans_twoDtct <= trans_twoDtct;    
         end
      end 
      else if ((cnt[4:0] == 5'd26) & (trans_twoDtct == 1'b0)) 
      begin
         if (tap_dly_reg[26] ~^ tap_dly_reg[27]) 
         begin
            if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
	      begin	 
               trans_twoDtct <= 1'b1;
	      end
	      else
	      begin		 
	         trans_oneDtct <= 1'b1;
	      end
         end 
         else 
         begin             
            trans_oneDtct <= trans_oneDtct;    
	      trans_twoDtct <= trans_twoDtct; 
         end
      end 
	else if ((cnt[4:0] == 5'd27) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[27] ~^ tap_dly_reg[28]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin		 
               trans_twoDtct <= 1'b1;
		end
		else
		begin		 
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin            
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 	
	else if ((cnt[4:0] == 5'd28) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[28] ~^ tap_dly_reg[29]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin		 
               trans_twoDtct <= 1'b1;
		end
		else
		begin		 
		   trans_oneDtct <= 1'b1;
		end
         end 
	   else 
	   begin             
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd29) & (trans_twoDtct == 1'b0))
	begin
	   if (tap_dly_reg[29] ~^ tap_dly_reg[30]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct) )
		begin		
               trans_twoDtct <= 1'b1;
		end
		else
		begin		 
		   trans_oneDtct <= 1'b1;
	      end
         end 
	   else 
	   begin          
            trans_oneDtct <= trans_oneDtct;    
		trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else if ((cnt[4:0] == 5'd30) & (trans_twoDtct == 1'b0)) 
	begin
         if (tap_dly_reg[30] ~^ tap_dly_reg[31]) 
	   begin
	      if((trans_oneDtct == 1'b1) && (enb_trans_two_dtct))
		begin		
               trans_twoDtct <= 1'b1;
	      end
	      else
		begin		
		   trans_oneDtct <= 1'b1;
	      end
         end 
	   else 
	   begin
            trans_oneDtct <= trans_oneDtct;    
	      trans_twoDtct <= trans_twoDtct;    
         end
      end 
	else
	begin
         trans_oneDtct <= trans_oneDtct;    				
	  trans_twoDtct <= trans_twoDtct;    				
	end
   end
   
//always @(posedge clk)
//begin
//   if(reset)
//      tapForDqs <= `defaultTap;
//   else if(cnt[4] && cnt[3] && cnt[2] && cnt[1] && cnt[0])	
//   begin
//      if((trans_oneDtct == 1'b0) || (trans_twoDtct == 1'b0) || (phase_cnt > 5'd12))
//         tapForDqs <= `tap6;
//      else if((phase_cnt < 5'd8)) 
//         tapForDqs <= `tap3;
//	  else if((phase_cnt < 5'd11)) 
//		 tapForDqs <= `tap4;
//	  else
//		 tapForDqs <= `tap5;
//   end
//   else
//      tapForDqs <= tapForDqs;
//end		

	
always @(posedge clk)
begin
   if(reset)
   	tapForDqs_rl <= `defaultTap;
   else if(cnt[4] && cnt[3] && cnt[2] && cnt[1] && cnt[0])	
   	begin
      if((trans_oneDtct == 1'b0) || (trans_twoDtct == 1'b0) || (phase_cnt > 5'd12))
      	tapForDqs_rl <= `tap6;
      else if((phase_cnt < 5'd8)) 
      	tapForDqs_rl <= `tap3;
	else if((phase_cnt < 5'd11)) 
		tapForDqs_rl <= `tap4;
	else
		tapForDqs_rl <= `tap5;
   	end
   else
      tapForDqs_rl <= tapForDqs_rl;
end		


always @(posedge clk)
begin
   if(reset)
      tapForDqs_tb <= `defaultTap;
   else if(cnt[4] && cnt[3] && cnt[2] && cnt[1] && cnt[0])	
   begin
      if((trans_oneDtct == 1'b0) || (trans_twoDtct == 1'b0) || (phase_cnt > 5'd14))
         tapForDqs_tb <= `tap6;
      else if((phase_cnt < 5'd10)) 
         tapForDqs_tb <= `tap1;
	  else if((phase_cnt < 5'd11)) 
	  	 tapForDqs_tb <= `tap2;
  	  else if((phase_cnt < 5'd12)) 
		 tapForDqs_tb <= `tap3;
  	  else if((phase_cnt < 5'd14)) 
		 tapForDqs_tb <= `tap4;
	  else
		 tapForDqs_tb <= `tap5;
   end
   else
      tapForDqs_tb <= tapForDqs_tb;
end


endmodule