📄 data_read_controller.v
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.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_81_rd_addr)
);
rd_gray_cntr fifo_90_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_90_rd_addr)
);
rd_gray_cntr fifo_91_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_91_rd_addr)
);
rd_gray_cntr fifo_100_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_100_rd_addr)
);
rd_gray_cntr fifo_101_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_101_rd_addr)
);
rd_gray_cntr fifo_110_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_110_rd_addr)
);
rd_gray_cntr fifo_111_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_111_rd_addr)
);
rd_gray_cntr fifo_120_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_120_rd_addr)
);
rd_gray_cntr fifo_121_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_121_rd_addr)
);
rd_gray_cntr fifo_130_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_130_rd_addr)
);
rd_gray_cntr fifo_131_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_131_rd_addr)
);
rd_gray_cntr fifo_140_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_140_rd_addr)
);
rd_gray_cntr fifo_141_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_141_rd_addr)
);
rd_gray_cntr fifo_150_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_150_rd_addr)
);
rd_gray_cntr fifo_151_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_151_rd_addr)
);
//-------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------------------------------------------------
//**************************************************************************************************
// DQS Internal Delay Circuit implemented in LUTs
//**************************************************************************************************
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay0_col0 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[0])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay0_col1 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[0])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay1_col0 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[1])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay1_col1 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[1])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay2_col0 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[2])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay2_col1 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[2])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay3_col0 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[3])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay3_col1 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[3])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay4_col0 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[4])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay4_col1 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[4])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay5_col0 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[5])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay5_col1 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[5])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay6_col0 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[6])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay6_col1 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[6])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay7_col0 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[7])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay7_col1 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[7])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay8_col0 (
.clk_in(dqs_int_delay_in8),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[8])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay8_col1 (
.clk_in(dqs_int_delay_in8),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[8])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay9_col0 (
.clk_in(dqs_int_delay_in9),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[9])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay9_col1 (
.clk_in(dqs_int_delay_in9),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[9])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay10_col0 (
.clk_in(dqs_int_delay_in10),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[10])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay10_col1 (
.clk_in(dqs_int_delay_in10),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[10])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay11_col0 (
.clk_in(dqs_int_delay_in11),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[11])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay11_col1 (
.clk_in(dqs_int_delay_in11),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[11])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay12_col0 (
.clk_in(dqs_int_delay_in12),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[12])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay12_col1 (
.clk_in(dqs_int_delay_in12),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[12])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay13_col0 (
.clk_in(dqs_int_delay_in13),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[13])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay13_col1 (
.clk_in(dqs_int_delay_in13),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[13])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay14_col0 (
.clk_in(dqs_int_delay_in14),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[14])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay14_col1 (
.clk_in(dqs_int_delay_in14),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[14])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay15_col0 (
.clk_in(dqs_int_delay_in15),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[15])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay15_col1 (
.clk_in(dqs_int_delay_in15),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[15])
);
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