cmp_data.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module cmp_data(
     clk,            
     data_valid,     
     lfsr_data,      
     read_data,      
     rst,            
     led_error_output, 
     data_valid_out 
     );

input  clk;
input  data_valid;
input  [255:0]lfsr_data/* synthesis syn_keep=1 */; 
input  [255:0]read_data;
input  rst;
output led_error_output;
output data_valid_out;


//attribute syn_keep : boolean;  -- Using Syn_Keep Derictive


reg  led_state;     
reg valid;
wire error;
wire [127:0]lfsr_0;
wire [127:0]lfsr_1;
wire [127:0]data_0;
wire [127:0]data_1;
reg  [3:0]byte_err;

wire valid_1;
reg [255:0]read_data_reg;

//attribute syn_keep of lfsr_data : signal is true;


always @ (posedge clk)
begin
  if (rst == 1'b1)
    read_data_reg <= 256'd0;
  else
    read_data_reg <= read_data;
end

always @ (posedge clk)
begin
  if (rst == 1'b1)
    begin

      valid   <= 1'b0;
    end
  else
    begin

      valid   <= data_valid;
    end
end
assign data_valid_out = valid;

assign data_0         = read_data_reg[127:0];
assign data_1         = read_data_reg[255:128];
			
assign lfsr_0         = lfsr_data[127:0];
assign lfsr_1         = lfsr_data[255:128];


//assign byte_err[0] =  (data_0[63:0]  != lfsr_0[63:0])   ? 1'b1 : 1'b0;
//assign byte_err[1] =  (data_0[127:64] != lfsr_0[127:64])  ? 1'b1 : 1'b0;
//assign byte_err[2] =  (data_1[63:0]  != lfsr_1[63:0])   ? 1'b1 : 1'b0;
//assign byte_err[3] =  (data_1[127:64] != lfsr_1[127:64])  ? 1'b1 : 1'b0;

always @ (posedge clk)
begin
	if (rst == 1'b1)
	  begin
            byte_err <= 4'b0000;
 
          end
	else
	  begin
                if (valid == 1'b1)
                  begin
			if (data_0[63:0] != lfsr_0[63:0])
				byte_err[0] <= 1'b1;
			else
				byte_err[0] <= 1'b0;
			if (data_0[127:64] != lfsr_0[127:64])
				byte_err[1] <= 1'b1;
			else
				byte_err[1] <= 1'b0;
			if (data_1[63:0] != lfsr_1[63:0])
				byte_err[2] <= 1'b1;
			else
				byte_err[2] <= 1'b0;
			if (data_1[127:64] != lfsr_1[127:64])
				byte_err[3] <= 1'b1;
			else
				byte_err[3] <= 1'b0;
		  end
		else
		  begin	
		  byte_err <= 4'b0000;
	          end
	  end
end

assign error = (byte_err[0] | byte_err[1] | byte_err[2] | byte_err[3]);

 // LED error output
always @ (posedge clk)
begin
      if (rst == 1'b1)
          led_state <= 1'b0;  // no error
      else
       begin
         case(led_state)
         1'b0 : begin
                if (error == 1'b1)
                 begin  
                      led_state <= 1'b1;  // Error
                      $display($time, " ### LED_ERROR : byte_err[0]= %b , byte_err[0]= %b ###",byte_err[0],byte_err[1]);
                      $finish;
                  end       
               else
                     led_state <= 1'b0;  // No Error
                end
          1'b1 : led_state <= 1'b1;
          default : led_state <= 1'b0;
         endcase
       end
end                   
assign led_error_output = (led_state == 1'b1) ? 1'b1 : 1'b0;
              

endmodule