📄 iobs.v
字号:
`timescale 1ns/100ps
module iobs (
SYS_CLK,
SYS_CLKb,
clk,
clk90,
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
ddr_rasb_cntrl,
ddr_casb_cntrl,
ddr_web_cntrl,
ddr_cke_cntrl,
ddr_csb_cntrl,
ddr_address_cntrl,
ddr_ba_cntrl,
rst_dqs_div_int,
dqs_reset,
dqs_enable,
ddr_dqs,
ddr_dq,
write_data_falling,
write_data_rising,
write_en_val,
reset90_r,
data_mask_f,
data_mask_r,
sys_clk_ibuf,
ddr1_clk0,
ddr1_clk0b,
ddr1_clk1,
ddr1_clk1b,
ddr1_clk2,
ddr1_clk2b,
ddr1_clk3,
ddr1_clk3b,
ddr1_clk4,
ddr1_clk4b,
ddr1_clk5,
ddr1_clk5b,
ddr1_clk6,
ddr1_clk6b,
ddr1_clk7,
ddr1_clk7b,
ddr_rasb,
ddr_casb,
ddr_web,
ddr_ba,
ddr_address,
ddr_cke,
ddr_csb,
rst_dqs_div1,
rst_dqs_div2,
rst_dqs_div_in1,
rst_dqs_div_in2,
rst_dqs_div_out1,
rst_dqs_div_out2,
dqs_int_delay_in0,
dqs_int_delay_in1,
dqs_int_delay_in2,
dqs_int_delay_in3,
dqs_int_delay_in4,
dqs_int_delay_in5,
dqs_int_delay_in6,
dqs_int_delay_in7,
dqs_int_delay_in8,
dqs_int_delay_in9,
dqs_int_delay_in10,
dqs_int_delay_in11,
dqs_int_delay_in12,
dqs_int_delay_in13,
dqs_int_delay_in14,
dqs_int_delay_in15,
dq,
ddr_dm
);
input SYS_CLK;
input SYS_CLKb;
input clk;
input clk90;
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
input ddr_rasb_cntrl;
input ddr_casb_cntrl;
input ddr_web_cntrl;
input ddr_cke_cntrl;
input ddr_csb_cntrl;
input [12:0]ddr_address_cntrl;
input [1:0]ddr_ba_cntrl;
input rst_dqs_div_int;
input dqs_reset;
input dqs_enable;
inout [15:0]ddr_dqs;
inout [127:0]ddr_dq;
input [127:0]write_data_falling;
input [127:0]write_data_rising;
input write_en_val;
input reset90_r;
input [15:0]data_mask_f;
input [15:0]data_mask_r;
output sys_clk_ibuf;
output ddr1_clk0;
output ddr1_clk0b;
output ddr1_clk1;
output ddr1_clk1b;
output ddr1_clk2;
output ddr1_clk2b;
output ddr1_clk3;
output ddr1_clk3b;
output ddr1_clk4;
output ddr1_clk4b;
output ddr1_clk5;
output ddr1_clk5b;
output ddr1_clk6;
output ddr1_clk6b;
output ddr1_clk7;
output ddr1_clk7b;
output ddr_rasb;
output ddr_casb;
output ddr_web;
output [1:0]ddr_ba;
output [12:0]ddr_address;
output ddr_cke;
output ddr_csb;
output rst_dqs_div1;
output rst_dqs_div2;
input rst_dqs_div_in1;
input rst_dqs_div_in2;
output rst_dqs_div_out1;
output rst_dqs_div_out2;
output dqs_int_delay_in0;
output dqs_int_delay_in1;
output dqs_int_delay_in2;
output dqs_int_delay_in3;
output dqs_int_delay_in4;
output dqs_int_delay_in5;
output dqs_int_delay_in6;
output dqs_int_delay_in7;
output dqs_int_delay_in8;
output dqs_int_delay_in9;
output dqs_int_delay_in10;
output dqs_int_delay_in11;
output dqs_int_delay_in12;
output dqs_int_delay_in13;
output dqs_int_delay_in14;
output dqs_int_delay_in15;
output [127:0]dq;
output [15:0]ddr_dm;
infrastructure_iobs infrastructure_iobs0 (
.SYS_CLK (SYS_CLK),
.SYS_CLKb (SYS_CLKb),
.clk0 (clk),
.clk90 (clk90),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.sys_clk_ibuf (sys_clk_ibuf),
.ddr1_clk0 (ddr1_clk0),
.ddr1_clk0b (ddr1_clk0b),
.ddr1_clk1 (ddr1_clk1),
.ddr1_clk1b (ddr1_clk1b),
.ddr1_clk2 (ddr1_clk2),
.ddr1_clk2b (ddr1_clk2b),
.ddr1_clk3 (ddr1_clk3),
.ddr1_clk3b (ddr1_clk3b),
.ddr1_clk4 (ddr1_clk4),
.ddr1_clk4b (ddr1_clk4b),
.ddr1_clk5 (ddr1_clk5),
.ddr1_clk5b (ddr1_clk5b),
.ddr1_clk6 (ddr1_clk6),
.ddr1_clk6b (ddr1_clk6b),
.ddr1_clk7 (ddr1_clk7),
.ddr1_clk7b (ddr1_clk7b)
);
controller_iobs controller_iobs0 (
.clk0 (clk),
//XST_REMOVECOMMENT .clk180 (clk180),
.ddr_rasb_cntrl (ddr_rasb_cntrl),
.ddr_casb_cntrl (ddr_casb_cntrl),
.ddr_web_cntrl (ddr_web_cntrl),
.ddr_cke_cntrl (ddr_cke_cntrl),
.ddr_csb_cntrl (ddr_csb_cntrl),
.ddr_address_cntrl (ddr_address_cntrl),
.ddr_ba_cntrl (ddr_ba_cntrl),
.rst_dqs_div_int (rst_dqs_div_int),
.ddr_rasb (ddr_rasb),
.ddr_casb (ddr_casb),
.ddr_web (ddr_web),
.ddr_ba (ddr_ba),
.ddr_address (ddr_address),
.ddr_cke (ddr_cke),
.ddr_csb (ddr_csb),
.rst_dqs_div1 (rst_dqs_div1),
.rst_dqs_div2 (rst_dqs_div2),
.rst_dqs_div_in1 (rst_dqs_div_in1),
.rst_dqs_div_in2 (rst_dqs_div_in2),
.rst_dqs_div_out1 (rst_dqs_div_out1),
.rst_dqs_div_out2 (rst_dqs_div_out2)
);
data_path_iobs datapath_iobs0 (
.clk (clk),
.clk90 (clk90),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.reset90_r (reset90_r),
.dqs_reset (dqs_reset),
.dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs),
.ddr_dq (ddr_dq),
.write_data_falling (write_data_falling),
.write_data_rising (write_data_rising),
.write_en_val (write_en_val),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.dqs_int_delay_in4 (dqs_int_delay_in4),
.dqs_int_delay_in5 (dqs_int_delay_in5),
.dqs_int_delay_in6 (dqs_int_delay_in6),
.dqs_int_delay_in7 (dqs_int_delay_in7),
.dqs_int_delay_in8 (dqs_int_delay_in8),
.dqs_int_delay_in9 (dqs_int_delay_in9),
.dqs_int_delay_in10 (dqs_int_delay_in10),
.dqs_int_delay_in11 (dqs_int_delay_in11),
.dqs_int_delay_in12 (dqs_int_delay_in12),
.dqs_int_delay_in13 (dqs_int_delay_in13),
.dqs_int_delay_in14 (dqs_int_delay_in14),
.dqs_int_delay_in15 (dqs_int_delay_in15),
.ddr_dq_val (dq),
.ddr_dm (ddr_dm)
);
endmodule
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