data_path_iobs.v

XILINX memory interface generator. XILINX的外部存储器接口。

      				.write_data_falling (write_data_falling[90]), 
      				.write_data_rising  (write_data_rising[90]),
      				.read_data_in       (ddr_dq_in[90]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob91 
				(
      				.ddr_dq_inout       (ddr_dq[91]), 
      				.write_data_falling (write_data_falling[91]), 
      				.write_data_rising  (write_data_rising[91]),
      				.read_data_in       (ddr_dq_in[91]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob92 
				(
      				.ddr_dq_inout       (ddr_dq[92]), 
      				.write_data_falling (write_data_falling[92]), 
      				.write_data_rising  (write_data_rising[92]),
      				.read_data_in       (ddr_dq_in[92]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob93 
				(
      				.ddr_dq_inout       (ddr_dq[93]), 
      				.write_data_falling (write_data_falling[93]), 
      				.write_data_rising  (write_data_rising[93]),
      				.read_data_in       (ddr_dq_in[93]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob94 
				(
      				.ddr_dq_inout       (ddr_dq[94]), 
      				.write_data_falling (write_data_falling[94]), 
      				.write_data_rising  (write_data_rising[94]),
      				.read_data_in       (ddr_dq_in[94]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
  
 ddr_dq_iob  ddr_dq_iob95 
				(
      				.ddr_dq_inout       (ddr_dq[95]), 
      				.write_data_falling (write_data_falling[95]), 
      				.write_data_rising  (write_data_rising[95]),
      				.read_data_in       (ddr_dq_in[95]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob96 
				(
      				.ddr_dq_inout       (ddr_dq[96]), 
      				.write_data_falling (write_data_falling[96]), 
      				.write_data_rising  (write_data_rising[96]),
      				.read_data_in       (ddr_dq_in[96]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
 ddr_dq_iob  ddr_dq_iob97 
				(
      				.ddr_dq_inout       (ddr_dq[97]), 
      				.write_data_falling (write_data_falling[97]), 
      				.write_data_rising  (write_data_rising[97]),
      				.read_data_in       (ddr_dq_in[97]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob98 
				(
      				.ddr_dq_inout       (ddr_dq[98]), 
      				.write_data_falling (write_data_falling[98]), 
      				.write_data_rising  (write_data_rising[98]),
      				.read_data_in       (ddr_dq_in[98]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob99 
				(
      				.ddr_dq_inout       (ddr_dq[99]), 
      				.write_data_falling (write_data_falling[99]), 
      				.write_data_rising  (write_data_rising[99]),
      				.read_data_in       (ddr_dq_in[99]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
ddr_dq_iob  ddr_dq_iob100 
				(
      				.ddr_dq_inout       (ddr_dq[100]), 
      				.write_data_falling (write_data_falling[100]), 
      				.write_data_rising  (write_data_rising[100]),
      				.read_data_in       (ddr_dq_in[100]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob101 
				(
      				.ddr_dq_inout       (ddr_dq[101]), 
      				.write_data_falling (write_data_falling[101]), 
      				.write_data_rising  (write_data_rising[101]),
      				.read_data_in       (ddr_dq_in[101]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob102 
				(
      				.ddr_dq_inout       (ddr_dq[102]), 
      				.write_data_falling (write_data_falling[102]), 
      				.write_data_rising  (write_data_rising[102]),
      				.read_data_in       (ddr_dq_in[102]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob103 
				(
      				.ddr_dq_inout       (ddr_dq[103]), 
      				.write_data_falling (write_data_falling[103]), 
      				.write_data_rising  (write_data_rising[103]),
      				.read_data_in       (ddr_dq_in[103]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob104 
				(
      				.ddr_dq_inout       (ddr_dq[104]), 
      				.write_data_falling (write_data_falling[104]), 
      				.write_data_rising  (write_data_rising[104]),
      				.read_data_in       (ddr_dq_in[104]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
  
 ddr_dq_iob  ddr_dq_iob105 
				(
      				.ddr_dq_inout       (ddr_dq[105]), 
      				.write_data_falling (write_data_falling[105]), 
      				.write_data_rising  (write_data_rising[105]),
      				.read_data_in       (ddr_dq_in[105]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob106 
				(
      				.ddr_dq_inout       (ddr_dq[106]), 
      				.write_data_falling (write_data_falling[106]), 
      				.write_data_rising  (write_data_rising[106]),
      				.read_data_in       (ddr_dq_in[106]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
 ddr_dq_iob  ddr_dq_iob107 
				(
      				.ddr_dq_inout       (ddr_dq[107]), 
      				.write_data_falling (write_data_falling[107]), 
      				.write_data_rising  (write_data_rising[107]),
      				.read_data_in       (ddr_dq_in[107]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob108 
				(
      				.ddr_dq_inout       (ddr_dq[108]), 
      				.write_data_falling (write_data_falling[108]), 
      				.write_data_rising  (write_data_rising[108]),
      				.read_data_in       (ddr_dq_in[108]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob109 
				(
      				.ddr_dq_inout       (ddr_dq[109]), 
      				.write_data_falling (write_data_falling[109]), 
      				.write_data_rising  (write_data_rising[109]),
      				.read_data_in       (ddr_dq_in[109]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );


ddr_dq_iob  ddr_dq_iob110 
				(
      				.ddr_dq_inout       (ddr_dq[110]), 
      				.write_data_falling (write_data_falling[110]), 
      				.write_data_rising  (write_data_rising[110]),
      				.read_data_in       (ddr_dq_in[110]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob111 
				(
      				.ddr_dq_inout       (ddr_dq[111]), 
      				.write_data_falling (write_data_falling[111]), 
      				.write_data_rising  (write_data_rising[111]),
      				.read_data_in       (ddr_dq_in[111]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob112 
				(
      				.ddr_dq_inout       (ddr_dq[112]), 
      				.write_data_falling (write_data_falling[112]), 
      				.write_data_rising  (write_data_rising[112]),
      				.read_data_in       (ddr_dq_in[112]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob113 
				(
      				.ddr_dq_inout       (ddr_dq[113]), 
      				.write_data_falling (write_data_falling[113]), 
      				.write_data_rising  (write_data_rising[113]),
      				.read_data_in       (ddr_dq_in[113]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob114 
				(
      				.ddr_dq_inout       (ddr_dq[114]), 
      				.write_data_falling (write_data_falling[114]), 
      				.write_data_rising  (write_data_rising[114]),
      				.read_data_in       (ddr_dq_in[114]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
  
 ddr_dq_iob  ddr_dq_iob115 
				(
      				.ddr_dq_inout       (ddr_dq[115]), 
      				.write_data_falling (write_data_falling[115]), 
      				.write_data_rising  (write_data_rising[115]),
      				.read_data_in       (ddr_dq_in[115]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob116 
				(
      				.ddr_dq_inout       (ddr_dq[116]), 
      				.write_data_falling (write_data_falling[116]), 
      				.write_data_rising  (write_data_rising[116]),
      				.read_data_in       (ddr_dq_in[116]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
 ddr_dq_iob  ddr_dq_iob117 
				(
      				.ddr_dq_inout       (ddr_dq[117]), 
      				.write_data_falling (write_data_falling[117]), 
      				.write_data_rising  (write_data_rising[117]),
      				.read_data_in       (ddr_dq_in[117]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),