📄 data_path_iobs.v
字号:
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob35
(
.ddr_dq_inout (ddr_dq[35]),
.write_data_falling (write_data_falling[35]),
.write_data_rising (write_data_rising[35]),
.read_data_in (ddr_dq_in[35]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob36
(
.ddr_dq_inout (ddr_dq[36]),
.write_data_falling (write_data_falling[36]),
.write_data_rising (write_data_rising[36]),
.read_data_in (ddr_dq_in[36]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob37
(
.ddr_dq_inout (ddr_dq[37]),
.write_data_falling (write_data_falling[37]),
.write_data_rising (write_data_rising[37]),
.read_data_in (ddr_dq_in[37]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob38
(
.ddr_dq_inout (ddr_dq[38]),
.write_data_falling (write_data_falling[38]),
.write_data_rising (write_data_rising[38]),
.read_data_in (ddr_dq_in[38]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob39
(
.ddr_dq_inout (ddr_dq[39]),
.write_data_falling (write_data_falling[39]),
.write_data_rising (write_data_rising[39]),
.read_data_in (ddr_dq_in[39]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob40
(
.ddr_dq_inout (ddr_dq[40]),
.write_data_falling (write_data_falling[40]),
.write_data_rising (write_data_rising[40]),
.read_data_in (ddr_dq_in[40]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob41
(
.ddr_dq_inout (ddr_dq[41]),
.write_data_falling (write_data_falling[41]),
.write_data_rising (write_data_rising[41]),
.read_data_in (ddr_dq_in[41]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob42
(
.ddr_dq_inout (ddr_dq[42]),
.write_data_falling (write_data_falling[42]),
.write_data_rising (write_data_rising[42]),
.read_data_in (ddr_dq_in[42]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob43
(
.ddr_dq_inout (ddr_dq[43]),
.write_data_falling (write_data_falling[43]),
.write_data_rising (write_data_rising[43]),
.read_data_in (ddr_dq_in[43]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob44
(
.ddr_dq_inout (ddr_dq[44]),
.write_data_falling (write_data_falling[44]),
.write_data_rising (write_data_rising[44]),
.read_data_in (ddr_dq_in[44]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob45
(
.ddr_dq_inout (ddr_dq[45]),
.write_data_falling (write_data_falling[45]),
.write_data_rising (write_data_rising[45]),
.read_data_in (ddr_dq_in[45]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob46
(
.ddr_dq_inout (ddr_dq[46]),
.write_data_falling (write_data_falling[46]),
.write_data_rising (write_data_rising[46]),
.read_data_in (ddr_dq_in[46]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob47
(
.ddr_dq_inout (ddr_dq[47]),
.write_data_falling (write_data_falling[47]),
.write_data_rising (write_data_rising[47]),
.read_data_in (ddr_dq_in[47]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob48
(
.ddr_dq_inout (ddr_dq[48]),
.write_data_falling (write_data_falling[48]),
.write_data_rising (write_data_rising[48]),
.read_data_in (ddr_dq_in[48]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob49
(
.ddr_dq_inout (ddr_dq[49]),
.write_data_falling (write_data_falling[49]),
.write_data_rising (write_data_rising[49]),
.read_data_in (ddr_dq_in[49]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob50
(
.ddr_dq_inout (ddr_dq[50]),
.write_data_falling (write_data_falling[50]),
.write_data_rising (write_data_rising[50]),
.read_data_in (ddr_dq_in[50]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob51
(
.ddr_dq_inout (ddr_dq[51]),
.write_data_falling (write_data_falling[51]),
.write_data_rising (write_data_rising[51]),
.read_data_in (ddr_dq_in[51]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob52
(
.ddr_dq_inout (ddr_dq[52]),
.write_data_falling (write_data_falling[52]),
.write_data_rising (write_data_rising[52]),
.read_data_in (ddr_dq_in[52]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob53
(
.ddr_dq_inout (ddr_dq[53]),
.write_data_falling (write_data_falling[53]),
.write_data_rising (write_data_rising[53]),
.read_data_in (ddr_dq_in[53]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob54
(
.ddr_dq_inout (ddr_dq[54]),
.write_data_falling (write_data_falling[54]),
.write_data_rising (write_data_rising[54]),
.read_data_in (ddr_dq_in[54]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob55
(
.ddr_dq_inout (ddr_dq[55]),
.write_data_falling (write_data_falling[55]),
.write_data_rising (write_data_rising[55]),
.read_data_in (ddr_dq_in[55]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob56
(
.ddr_dq_inout (ddr_dq[56]),
.write_data_falling (write_data_falling[56]),
.write_data_rising (write_data_rising[56]),
.read_data_in (ddr_dq_in[56]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob57
(
.ddr_dq_inout (ddr_dq[57]),
.write_data_falling (write_data_falling[57]),
.write_data_rising (write_data_rising[57]),
.read_data_in (ddr_dq_in[57]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob58
(
.ddr_dq_inout (ddr_dq[58]),
.write_data_falling (write_data_falling[58]),
.write_data_rising (write_data_rising[58]),
.read_data_in (ddr_dq_in[58]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob59
(
.ddr_dq_inout (ddr_dq[59]),
.write_data_falling (write_data_falling[59]),
.write_data_rising (write_data_rising[59]),
.read_data_in (ddr_dq_in[59]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob60
(
.ddr_dq_inout (ddr_dq[60]),
.write_data_falling (write_data_falling[60]),
.write_data_rising (write_data_rising[60]),
.read_data_in (ddr_dq_in[60]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob61
(
.ddr_dq_inout (ddr_dq[61]),
.write_data_falling (write_data_falling[61]),
.write_data_rising (write_data_rising[61]),
.read_data_in (ddr_dq_in[61]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob62
(
.ddr_dq_inout (ddr_dq[62]),
.write_data_falling (write_data_falling[62]),
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