data_read_controller_24bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

assign fifo_11_rd_addr_val=fifo_11_rd_addr;
assign fifo_20_rd_addr_val=fifo_20_rd_addr;
assign fifo_21_rd_addr_val=fifo_21_rd_addr;

// FIFO WRITE POINTER DELAYED SIGNALS
// To avoid meta-stability due to the domain crossing from ddr_dqs to clk90 

always@(posedge clk90)
begin
   if (reset90_r == 1'b1)
        begin
	fifo_00_wr_addr_d <= 4'h0;
	fifo_01_wr_addr_d <= 4'h0;
  	end
    else                                                   
    	begin
    	fifo_00_wr_addr_d <= fifo_00_wr_addr;
	fifo_01_wr_addr_d <= fifo_01_wr_addr;
	end
end

// FIFO WRITE POINTER DOUBLE DELAYED SIGNALS

always@(posedge clk90)
begin
   if (reset90_r == 1'b1) 
        begin
	fifo_00_wr_addr_2d <= 4'h0;
	fifo_01_wr_addr_2d <= 4'h0;
	end
    else                                                   
    	begin
    	fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
	fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
	end
 end
 
// user data valid output signal from data path.

always@(posedge clk90)
begin
   if (reset90_r ==1'b1)
   	u_data_val	<= 1'b0;
   else
        u_data_val  <= read_valid_data_0_1;
end	



dqs_delay rst_dqs_div_delayed   (                                                                          
	                              .clk_in   (rst_dqs_div_in),
	                              .sel_in   (delay_sel),                                
	                              .clk_out  (rst_dqs_div)                              
	                             );


//*****************************************************************************************************
// fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )  
//*****************************************************************************************************

rd_gray_cntr fifo_00_rd_addr_inst  (
				.clk      (clk90),
				.reset    (reset90_r),
				.cnt_en   (read_valid_data_1_val),
				.rgc_gcnt (fifo_00_rd_addr)
				  ); 
				  
rd_gray_cntr fifo_01_rd_addr_inst  (
				.clk      (clk90),
				.reset    (reset90_r),
				.cnt_en   (read_valid_data_1_val),
				.rgc_gcnt (fifo_01_rd_addr)
				);                                                                         
rd_gray_cntr fifo_10_rd_addr_inst  (
				.clk      (clk90),
				.reset    (reset90_r),
				.cnt_en   (read_valid_data_1_val),
				.rgc_gcnt (fifo_10_rd_addr)
				  ); 
				  
rd_gray_cntr fifo_11_rd_addr_inst  (
				.clk      (clk90),
				.reset    (reset90_r),
				.cnt_en   (read_valid_data_1_val),
				.rgc_gcnt (fifo_11_rd_addr)
				);                                                                         
rd_gray_cntr fifo_20_rd_addr_inst  (
				.clk      (clk90),
				.reset    (reset90_r),
				.cnt_en   (read_valid_data_1_val),
				.rgc_gcnt (fifo_20_rd_addr)
				  ); 
				  
rd_gray_cntr fifo_21_rd_addr_inst  (
				.clk      (clk90),
				.reset    (reset90_r),
				.cnt_en   (read_valid_data_1_val),
				.rgc_gcnt (fifo_21_rd_addr)
				);                                                                         
//-------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------ 
//**************************************************************************************************
// DQS Internal Delay Circuit implemented in LUTs
//**************************************************************************************************

// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay dqs_delay0_col0  (                                                                          
                           .clk_in(dqs_int_delay_in0),
                           .sel_in(delay_sel),                                
                           .clk_out(dqs_delayed_col0[0])                               
                            );

// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs                               
dqs_delay dqs_delay0_col1  (                                                                          
                           .clk_in(dqs_int_delay_in0),
                           .sel_in(delay_sel),                                
                           .clk_out(dqs_delayed_col1[0])                               
                            );

// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay dqs_delay1_col0  (                                                                          
                           .clk_in(dqs_int_delay_in1),
                           .sel_in(delay_sel),                                
                           .clk_out(dqs_delayed_col0[1])                               
                            );

// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs                               
dqs_delay dqs_delay1_col1  (                                                                          
                           .clk_in(dqs_int_delay_in1),
                           .sel_in(delay_sel),                                
                           .clk_out(dqs_delayed_col1[1])                               
                            );

// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                               
dqs_delay dqs_delay2_col0  (                                                                          
                           .clk_in(dqs_int_delay_in2),
                           .sel_in(delay_sel),                                
                           .clk_out(dqs_delayed_col0[2])                               
                            );

// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs                               
dqs_delay dqs_delay2_col1  (                                                                          
                           .clk_in(dqs_int_delay_in2),
                           .sel_in(delay_sel),                                
                           .clk_out(dqs_delayed_col1[2])                               
                            );

//*****************************************************************************************************
// FIFO Write enable signal generation
//*****************************************************************************************************

 fifo_0_wr_en fifo_00_wr_en_inst (
				.clk             (dqs0_delayed_col1_n),
				.reset           (reset_r),
				.din             (rst_dqs_div),
				.rst_dqs_delay_n (rst_dqs_delay_0_n),
				.dout            (fifo_00_wr_en)
                          			   );
                          			   
 fifo_1_wr_en fifo_01_wr_en_inst (
				.clk		 (dqs0_delayed_col0),
				.rst_dqs_delay_n (rst_dqs_delay_0_n),
				.reset           (reset_r),
				.din             (rst_dqs_div),
				.dout            (fifo_01_wr_en)
				  );

 fifo_0_wr_en fifo_10_wr_en_inst (
				.clk             (dqs1_delayed_col1_n),
				.reset           (reset_r),
				.din             (rst_dqs_div),
				.rst_dqs_delay_n (rst_dqs_delay_1_n),
				.dout            (fifo_10_wr_en)
                          			   );
                          			   
 fifo_1_wr_en fifo_11_wr_en_inst (
				.clk		 (dqs1_delayed_col0),
				.rst_dqs_delay_n (rst_dqs_delay_1_n),
				.reset           (reset_r),
				.din             (rst_dqs_div),
				.dout            (fifo_11_wr_en)
				  );

 fifo_0_wr_en fifo_20_wr_en_inst (
				.clk             (dqs2_delayed_col1_n),
				.reset           (reset_r),
				.din             (rst_dqs_div),
				.rst_dqs_delay_n (rst_dqs_delay_2_n),
				.dout            (fifo_20_wr_en)
                          			   );
                          			   
 fifo_1_wr_en fifo_21_wr_en_inst (
				.clk		 (dqs2_delayed_col0),
				.rst_dqs_delay_n (rst_dqs_delay_2_n),
				.reset           (reset_r),
				.din             (rst_dqs_div),
				.dout            (fifo_21_wr_en)
				  );

//-------------------------------------------------------------------------------------------------
// write pointer gray counter instances 
//-------------------------------------------------------------------------------------------------

 wr_gray_cntr fifo_00_wr_addr_inst  (
				    .clk	     (dqs0_delayed_col1),
				    .reset	   (reset_r),
				    .cnt_en	  (fifo_00_wr_en),
				    .wgc_gcnt	(fifo_00_wr_addr)
				    );

 wr_gray_cntr fifo_01_wr_addr_inst  (
				    .clk 	    (dqs0_delayed_col0_n),
				    .reset	   (reset_r),
				    .cnt_en	  (fifo_01_wr_en),
				    .wgc_gcnt	(fifo_01_wr_addr)
                                				);

 wr_gray_cntr fifo_10_wr_addr_inst  (
				    .clk	     (dqs1_delayed_col1),
				    .reset	   (reset_r),
				    .cnt_en	  (fifo_10_wr_en),
				    .wgc_gcnt	(fifo_10_wr_addr)
				    );

 wr_gray_cntr fifo_11_wr_addr_inst  (
				    .clk 	    (dqs1_delayed_col0_n),
				    .reset	   (reset_r),
				    .cnt_en	  (fifo_11_wr_en),
				    .wgc_gcnt	(fifo_11_wr_addr)
                                				);

 wr_gray_cntr fifo_20_wr_addr_inst  (
				    .clk	     (dqs2_delayed_col1),
				    .reset	   (reset_r),
				    .cnt_en	  (fifo_20_wr_en),
				    .wgc_gcnt	(fifo_20_wr_addr)
				    );

 wr_gray_cntr fifo_21_wr_addr_inst  (
				    .clk 	    (dqs2_delayed_col0_n),
				    .reset	   (reset_r),
				    .cnt_en	  (fifo_21_wr_en),
				    .wgc_gcnt	(fifo_21_wr_addr)
                                				);
endmodule