data_read_controller_24bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*********************************************************************
// DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins

// In the current DATA PATH logic DATA CAPTURE part was modified.
// The below changes were made to reduce the resources in 
// the data capture

// in the current architecture data ( dq ) from ddr memory 
// directly stored into the FIFO's.

// Architectural changes :

// Used only TWO FIFOs ( instead of FOUR FIFOs ) 
// Used Single col ( col0 ) dqs_delayed_col signals
// Used Gray Counters for write and read pointers of the FIFOs 

// fbit stage is removed from ddr1_dqbit module ( in the data capture )
// dq_clk stage was removed 
// dqs_clk_div logic was removed
// ddr1_transfer_done logic was removed 
// data valid signals registering in clk90 domain was removed

// fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
// only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
// write enable for the FIFOs derived from rst_dqs_div signal


// Code revised by 	: Narayana Murty.
// Date 			      : Nov 18, 2003. 

//*********************************************************************
  `timescale 1ns/100ps
module    data_read_controller_24bit   ( 

     clk,                
     clk90,              
     reset_r,            
     reset90_r,          
     reset180_r,         
     reset270_r,         
     rst_dqs_div_in,     
     delay_sel,          
     dqs_int_delay_in0,  
     dqs_int_delay_in1,  
     dqs_int_delay_in2,   
     fifo_00_rd_addr_val,      
     fifo_01_rd_addr_val,      
     fifo_10_rd_addr_val,      
     fifo_11_rd_addr_val,      
     fifo_20_rd_addr_val,      
     fifo_21_rd_addr_val,      
     u_data_val,   			
     read_valid_data_1_val, 
     fifo_00_wr_en_val,			  
     fifo_10_wr_en_val,			  
     fifo_20_wr_en_val,			  
     fifo_01_wr_en_val,			  
     fifo_11_wr_en_val,			  
     fifo_21_wr_en_val,			  
     fifo_00_wr_addr_val,   
     fifo_01_wr_addr_val,   
     fifo_10_wr_addr_val,   
     fifo_11_wr_addr_val,   
     fifo_20_wr_addr_val,   
     fifo_21_wr_addr_val,   
     dqs0_delayed_col1_val, 
     dqs1_delayed_col1_val, 
     dqs2_delayed_col1_val, 
     dqs0_delayed_col0_n_val,
     dqs1_delayed_col0_n_val,
     dqs2_delayed_col0_n_val
      );

input     clk;
input     clk90;              
input     reset_r;           
input     reset90_r;        
input     reset180_r;        
input     reset270_r;        
input     rst_dqs_div_in;     
input     [4:0]delay_sel;          
input     dqs_int_delay_in0; 
input     dqs_int_delay_in1;  
input     dqs_int_delay_in2;  

output     [3:0]fifo_00_rd_addr_val;      
output     [3:0]fifo_01_rd_addr_val;     
output     [3:0]fifo_10_rd_addr_val;      
output     [3:0]fifo_11_rd_addr_val;     
output     [3:0]fifo_20_rd_addr_val;      
output     [3:0]fifo_21_rd_addr_val;     

output     u_data_val;   			
output     read_valid_data_1_val;  
     
output     fifo_00_wr_en_val;			  
output     fifo_10_wr_en_val;			  
output     fifo_20_wr_en_val;			 

output     fifo_01_wr_en_val;			  
output     fifo_11_wr_en_val;			  
output     fifo_21_wr_en_val;			  

output     [3:0]fifo_00_wr_addr_val;   
output     [3:0]fifo_01_wr_addr_val;    
output     [3:0]fifo_10_wr_addr_val;    
output     [3:0]fifo_11_wr_addr_val;    
output     [3:0]fifo_20_wr_addr_val;    
output     [3:0]fifo_21_wr_addr_val;    
     
output     dqs0_delayed_col1_val; 
output     dqs1_delayed_col1_val; 
output     dqs2_delayed_col1_val;  

output     dqs0_delayed_col0_n_val;
output     dqs1_delayed_col0_n_val;
output     dqs2_delayed_col0_n_val;

reg        u_data_val;
wire dqs_int_delay_in0;
wire dqs_int_delay_in1;
wire dqs_int_delay_in2;

wire [2:0]dqs_delayed_col0;
wire [2:0]dqs_delayed_col1;

wire resetn;

wire fifo_00_empty;
wire fifo_01_empty;

wire [3:0] fifo_00_wr_addr;
wire [3:0] fifo_01_wr_addr;
wire [3:0] fifo_10_wr_addr;
wire [3:0] fifo_11_wr_addr;
wire [3:0] fifo_20_wr_addr;
wire [3:0] fifo_21_wr_addr;

wire read_valid_data_0_1;
wire read_valid_data_1; 

wire dqs0_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0/* synthesis syn_keep=1 */;
wire dqs2_delayed_col0/* synthesis syn_keep=1 */;

wire dqs0_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs1_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs2_delayed_col1 /* synthesis syn_keep=1 */;	

wire dqs0_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs2_delayed_col0_n /* synthesis syn_keep=1 */;

wire dqs0_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs2_delayed_col1_n /* synthesis syn_keep=1 */;

//wire rst_dqs_div /* synthesis syn_keep=1 */;

wire 	   TIE_HIGH;

// FIFO WRITE ENABLE SIGNALS

wire 	fifo_00_wr_en;
wire 	fifo_01_wr_en;
wire 	fifo_10_wr_en;
wire 	fifo_11_wr_en;
wire 	fifo_20_wr_en;
wire 	fifo_21_wr_en;

//signal rst_dqs_delay_n : std_logic;

wire rst_dqs_delay_0_n;
wire rst_dqs_delay_1_n;
wire rst_dqs_delay_2_n;

// FIFO_WR_POINTER Delayed signals in clk90 domain

wire [3:0]fifo_00_rd_addr;
wire [3:0]fifo_01_rd_addr;
wire [3:0]fifo_10_rd_addr;
wire [3:0]fifo_11_rd_addr;
wire [3:0]fifo_20_rd_addr;
wire [3:0]fifo_21_rd_addr;

reg [3:0]fifo_00_wr_addr_d;
reg [3:0]fifo_00_wr_addr_2d;
reg [3:0]fifo_01_wr_addr_d;
reg [3:0]fifo_01_wr_addr_2d;

assign  fifo_00_wr_addr_val = fifo_00_wr_addr; 
assign fifo_01_wr_addr_val = fifo_01_wr_addr; 
assign fifo_10_wr_addr_val = fifo_10_wr_addr; 
assign fifo_11_wr_addr_val = fifo_11_wr_addr; 
assign fifo_20_wr_addr_val = fifo_20_wr_addr; 
assign fifo_21_wr_addr_val = fifo_21_wr_addr; 

assign fifo_00_wr_en_val		  =	fifo_00_wr_en;
assign fifo_10_wr_en_val		  =	fifo_10_wr_en;
assign fifo_20_wr_en_val		  =	fifo_20_wr_en;
 
assign fifo_01_wr_en_val		  =	fifo_01_wr_en;
assign fifo_11_wr_en_val		  =	fifo_11_wr_en;
assign fifo_21_wr_en_val		  =	fifo_21_wr_en;

assign dqs0_delayed_col1_val = dqs0_delayed_col1;
assign dqs1_delayed_col1_val = dqs1_delayed_col1;
assign dqs2_delayed_col1_val = dqs2_delayed_col1;

assign dqs0_delayed_col0_n_val =dqs0_delayed_col0_n;
assign dqs1_delayed_col0_n_val =dqs1_delayed_col0_n;
assign dqs2_delayed_col0_n_val =dqs2_delayed_col0_n;

///////////////////////////////////////////////////////////////////////////
assign dqs0_delayed_col0 = dqs_delayed_col0[0];
assign dqs1_delayed_col0 = dqs_delayed_col0[1];
assign dqs2_delayed_col0 = dqs_delayed_col0[2];

assign dqs0_delayed_col1 = dqs_delayed_col1[0];
assign dqs1_delayed_col1 = dqs_delayed_col1[1];
assign dqs2_delayed_col1 = dqs_delayed_col1[2];

// dqsx_delayed_col0 negated signals

assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
assign dqs2_delayed_col0_n = ~ dqs2_delayed_col0;

// dqsx_delayed_col1 negated signals

assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
assign dqs1_delayed_col1_n = ~ dqs1_delayed_col1;
assign dqs2_delayed_col1_n = ~ dqs2_delayed_col1;

// TIE_HIGH assignment
assign TIE_HIGH = 1'b1;
assign  resetn  = ~ reset_r;
assign read_valid_data_0_1 = ( (~fifo_00_empty) && (~fifo_01_empty) );
assign read_valid_data_1_val   = read_valid_data_0_1;

assign  fifo_00_empty  = (fifo_00_rd_addr[3:0] == fifo_00_wr_addr_2d[3:0] )? 1'b1 :1'b0;
assign fifo_01_empty   = (fifo_01_rd_addr[3:0] == fifo_01_wr_addr_2d[3:0] )? 1'b1 :1'b0;

assign fifo_00_rd_addr_val=fifo_00_rd_addr;
assign fifo_01_rd_addr_val=fifo_01_rd_addr;
assign fifo_10_rd_addr_val=fifo_10_rd_addr;