📄 data_path_24bit.v
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`timescale 1ns/100ps
`include "parameters_24bit.v"
module data_path_24bit (
user_input_data,
user_data_mask,
clk,
clk90,
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
reset,
reset90,
reset180,
reset270,
write_enable,
rst_dqs_div_in,
delay_sel,
dqs_int_delay_in0,
dqs_int_delay_in1,
dqs_int_delay_in2,
dqs_int_delay_in3,
dqs_int_delay_in4,
dqs_int_delay_in5,
dq,
u_data_val,
user_output_data,
write_en_val,
reset90_r_val,
data_mask_f,
data_mask_r,
write_data_falling,
write_data_rising
);
input [47:0]user_input_data;
input [((`mask_width)-1):0] user_data_mask;
input clk;
input clk90;
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
input reset;
input reset90;
input reset180;
input reset270;
input write_enable;
input rst_dqs_div_in;
input [4:0]delay_sel;
input dqs_int_delay_in0;
input dqs_int_delay_in1;
input dqs_int_delay_in2;
input dqs_int_delay_in3;
input dqs_int_delay_in4;
input dqs_int_delay_in5;
input [23:0]dq;
output u_data_val;
output [47:0]user_output_data;
output write_en_val;
output reset90_r_val;
output [((`mask_width/2)-1):0] data_mask_f;
output [((`mask_width/2)-1):0] data_mask_r;
output [23:0]write_data_falling;
output [23:0]write_data_rising;
wire reset_r;
wire reset90_r;
wire reset180_r;
wire reset270_r;
wire [3:0]fifo_00_rd_addr;
wire [3:0]fifo_01_rd_addr;
wire [3:0]fifo_10_rd_addr;
wire [3:0]fifo_11_rd_addr;
wire [3:0]fifo_20_rd_addr;
wire [3:0]fifo_21_rd_addr;
wire [3:0]fifo_30_rd_addr;
wire [3:0]fifo_31_rd_addr;
wire [3:0]fifo_40_rd_addr;
wire [3:0]fifo_41_rd_addr;
wire [3:0]fifo_50_rd_addr;
wire [3:0]fifo_51_rd_addr;
wire read_valid_data_1;
wire [3:0]fifo_00_wr_addr;
wire [3:0]fifo_01_wr_addr;
wire [3:0]fifo_10_wr_addr;
wire [3:0]fifo_11_wr_addr;
wire [3:0]fifo_20_wr_addr;
wire [3:0]fifo_21_wr_addr;
wire [3:0]fifo_30_wr_addr;
wire [3:0]fifo_31_wr_addr;
wire [3:0]fifo_40_wr_addr;
wire [3:0]fifo_41_wr_addr;
wire [3:0]fifo_50_wr_addr;
wire [3:0]fifo_51_wr_addr;
wire fifo_00_wr_en;
wire fifo_10_wr_en;
wire fifo_20_wr_en;
wire fifo_30_wr_en;
wire fifo_40_wr_en;
wire fifo_50_wr_en;
wire fifo_01_wr_en;
wire fifo_11_wr_en;
wire fifo_21_wr_en;
wire fifo_31_wr_en;
wire fifo_41_wr_en;
wire fifo_51_wr_en;
wire dqs0_delayed_col1;
wire dqs1_delayed_col1;
wire dqs2_delayed_col1;
wire dqs3_delayed_col1;
wire dqs4_delayed_col1;
wire dqs5_delayed_col1;
wire dqs0_delayed_col0_n;
wire dqs1_delayed_col0_n;
wire dqs2_delayed_col0_n;
wire dqs3_delayed_col0_n;
wire dqs4_delayed_col0_n;
wire dqs5_delayed_col0_n;
assign reset90_r_val = reset90_r;
data_read_24bit data_read0 (
.clk (clk),
.clk90 (clk90),
.reset90_r (reset90_r),
.reset270_r (reset270_r),
.ddr_dq_in (dq),
.read_valid_data_1 (read_valid_data_1),
.fifo_00_wr_en (fifo_00_wr_en),
.fifo_10_wr_en (fifo_10_wr_en),
.fifo_20_wr_en (fifo_20_wr_en),
.fifo_30_wr_en (fifo_30_wr_en),
.fifo_40_wr_en (fifo_40_wr_en),
.fifo_50_wr_en (fifo_50_wr_en),
.fifo_01_wr_en (fifo_01_wr_en),
.fifo_11_wr_en (fifo_11_wr_en),
.fifo_21_wr_en (fifo_21_wr_en),
.fifo_31_wr_en (fifo_31_wr_en),
.fifo_41_wr_en (fifo_41_wr_en),
.fifo_51_wr_en (fifo_51_wr_en),
.fifo_00_wr_addr (fifo_00_wr_addr),
.fifo_01_wr_addr (fifo_01_wr_addr),
.fifo_10_wr_addr (fifo_10_wr_addr),
.fifo_11_wr_addr (fifo_11_wr_addr),
.fifo_20_wr_addr (fifo_20_wr_addr),
.fifo_21_wr_addr (fifo_21_wr_addr),
.fifo_30_wr_addr (fifo_30_wr_addr),
.fifo_31_wr_addr (fifo_31_wr_addr),
.fifo_40_wr_addr (fifo_40_wr_addr),
.fifo_41_wr_addr (fifo_41_wr_addr),
.fifo_50_wr_addr (fifo_50_wr_addr),
.fifo_51_wr_addr (fifo_51_wr_addr),
.dqs0_delayed_col1 (dqs0_delayed_col1),
.dqs1_delayed_col1 (dqs1_delayed_col1),
.dqs2_delayed_col1 (dqs2_delayed_col1),
.dqs3_delayed_col1 (dqs3_delayed_col1),
.dqs4_delayed_col1 (dqs4_delayed_col1),
.dqs5_delayed_col1 (dqs5_delayed_col1),
.dqs0_delayed_col0_n (dqs0_delayed_col0_n),
.dqs1_delayed_col0_n (dqs1_delayed_col0_n),
.dqs2_delayed_col0_n (dqs2_delayed_col0_n),
.dqs3_delayed_col0_n (dqs3_delayed_col0_n),
.dqs4_delayed_col0_n (dqs4_delayed_col0_n),
.dqs5_delayed_col0_n (dqs5_delayed_col0_n),
.user_output_data (user_output_data),
.fifo_00_rd_addr (fifo_00_rd_addr),
.fifo_01_rd_addr (fifo_01_rd_addr),
.fifo_10_rd_addr (fifo_10_rd_addr),
.fifo_11_rd_addr (fifo_11_rd_addr),
.fifo_20_rd_addr (fifo_20_rd_addr),
.fifo_21_rd_addr (fifo_21_rd_addr),
.fifo_30_rd_addr (fifo_30_rd_addr),
.fifo_31_rd_addr (fifo_31_rd_addr),
.fifo_40_rd_addr (fifo_40_rd_addr),
.fifo_41_rd_addr (fifo_41_rd_addr),
.fifo_50_rd_addr (fifo_50_rd_addr),
.fifo_51_rd_addr (fifo_51_rd_addr)
);
data_read_controller_24bit data_read_controller0 (
.clk (clk),
.clk90 (clk90),
.reset_r (reset_r),
.reset90_r (reset90_r),
.reset180_r (reset180_r),
.reset270_r (reset270_r),
.rst_dqs_div_in (rst_dqs_div_in),
.delay_sel (delay_sel),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.dqs_int_delay_in4 (dqs_int_delay_in4),
.dqs_int_delay_in5 (dqs_int_delay_in5),
.fifo_00_rd_addr_val (fifo_00_rd_addr),
.fifo_01_rd_addr_val (fifo_01_rd_addr),
.fifo_10_rd_addr_val (fifo_10_rd_addr),
.fifo_11_rd_addr_val (fifo_11_rd_addr),
.fifo_20_rd_addr_val (fifo_20_rd_addr),
.fifo_21_rd_addr_val (fifo_21_rd_addr),
.fifo_30_rd_addr_val (fifo_30_rd_addr),
.fifo_31_rd_addr_val (fifo_31_rd_addr),
.fifo_40_rd_addr_val (fifo_40_rd_addr),
.fifo_41_rd_addr_val (fifo_41_rd_addr),
.fifo_50_rd_addr_val (fifo_50_rd_addr),
.fifo_51_rd_addr_val (fifo_51_rd_addr),
.u_data_val (u_data_val),
.read_valid_data_1_val (read_valid_data_1),
.fifo_00_wr_en_val (fifo_00_wr_en),
.fifo_10_wr_en_val (fifo_10_wr_en),
.fifo_20_wr_en_val (fifo_20_wr_en),
.fifo_30_wr_en_val (fifo_30_wr_en),
.fifo_40_wr_en_val (fifo_40_wr_en),
.fifo_50_wr_en_val (fifo_50_wr_en),
.fifo_01_wr_en_val (fifo_01_wr_en),
.fifo_11_wr_en_val (fifo_11_wr_en),
.fifo_21_wr_en_val (fifo_21_wr_en),
.fifo_31_wr_en_val (fifo_31_wr_en),
.fifo_41_wr_en_val (fifo_41_wr_en),
.fifo_51_wr_en_val (fifo_51_wr_en),
.fifo_00_wr_addr_val (fifo_00_wr_addr),
.fifo_01_wr_addr_val (fifo_01_wr_addr),
.fifo_10_wr_addr_val (fifo_10_wr_addr),
.fifo_11_wr_addr_val (fifo_11_wr_addr),
.fifo_20_wr_addr_val (fifo_20_wr_addr),
.fifo_21_wr_addr_val (fifo_21_wr_addr),
.fifo_30_wr_addr_val (fifo_30_wr_addr),
.fifo_31_wr_addr_val (fifo_31_wr_addr),
.fifo_40_wr_addr_val (fifo_40_wr_addr),
.fifo_41_wr_addr_val (fifo_41_wr_addr),
.fifo_50_wr_addr_val (fifo_50_wr_addr),
.fifo_51_wr_addr_val (fifo_51_wr_addr),
.dqs0_delayed_col1_val ( dqs0_delayed_col1),
.dqs1_delayed_col1_val ( dqs1_delayed_col1),
.dqs2_delayed_col1_val ( dqs2_delayed_col1),
.dqs3_delayed_col1_val ( dqs3_delayed_col1),
.dqs4_delayed_col1_val ( dqs4_delayed_col1),
.dqs5_delayed_col1_val ( dqs5_delayed_col1),
.dqs0_delayed_col0_n_val ( dqs0_delayed_col0_n),
.dqs1_delayed_col0_n_val ( dqs1_delayed_col0_n),
.dqs2_delayed_col0_n_val ( dqs2_delayed_col0_n),
.dqs3_delayed_col0_n_val ( dqs3_delayed_col0_n),
.dqs4_delayed_col0_n_val ( dqs4_delayed_col0_n),
.dqs5_delayed_col0_n_val ( dqs5_delayed_col0_n)
);
data_write_24bit data_write0 (
.user_input_data ( user_input_data),
.user_data_mask ( user_data_mask ),
.clk90 ( clk90),
.reset90_r (reset90_r),
.reset270_r (reset270_r),
.write_enable ( write_enable),
.write_en_val ( write_en_val),
.write_data_falling ( write_data_falling),
.write_data_rising ( write_data_rising),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r)
);
data_path_rst data_path_rst0 (
.clk (clk),
.clk90 ( clk90),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.reset (reset),
.reset90 (reset90),
.reset180 (reset180),
.reset270 (reset270),
.reset_r (reset_r),
.reset90_r (reset90_r),
.reset180_r (reset180_r),
.reset270_r (reset270_r)
);
endmodule⌨️ 快捷键说明
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