ddr1_top_24bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

`include "parameters_24bit.v"
`timescale 1ns/100ps
module    ddr1_top_24bit   ( 

     dip1,                  
     dip3,                  
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
       clk_int,
       clk90_int,
       delay_sel_val,
       sys_rst90,
       sys_rst180,
       sys_rst270,
       rst_dqs_div_in,
     rst_dqs_div_out,  					
     reset_in,              
     user_input_data,       
       user_data_mask,      
     user_output_data,      
     user_data_valid,      
     user_input_address,   
      user_bank_address,    
     user_config_register,  
     user_command_register, 
     user_cmd_ack,          
     burst_done,
     init_val,              
     ar_done,               
     ddr_dqs,               
     ddr_dq,                
     ddr_cke,               
     ddr_csb,               
     ddr_rasb,              
     ddr_casb,              
     ddr_web,               
     ddr_dm,                
     ddr_ba,                
     ddr_address,           
auto_ref_req,  
wait_200us, 
     ddr1_clk0,             
     ddr1_clk0b,            
     ddr1_clk1,             
     ddr1_clk1b,            
       sys_rst
     );
     
     
input     dip1;
 input     dip3;
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
 input     rst_dqs_div_in;
 output	  rst_dqs_div_out;
input       clk_int;
input       clk90_int;
input       reset_in;
input      [4:0] delay_sel_val;
input       sys_rst;
input       sys_rst90;
input       sys_rst180;
input       sys_rst270;
input     [47:0]user_input_data;
input     [((`mask_width)-1):0] user_data_mask;
output    [47:0]user_output_data;

output    user_data_valid;
input     [((`row_address + `column_address)-1):0]user_input_address; 
input     [`bank_address-1:0]user_bank_address;   
input     [9:0]user_config_register;
input     [2:0]user_command_register;
output    user_cmd_ack;          
input     burst_done;           
 		   
output    init_val;        
output    ar_done;         
inout     [2:0]ddr_dqs;
inout     [23:0]ddr_dq;
output     ddr_cke;              
output     ddr_csb;              
output    auto_ref_req;  
input    wait_200us; 
output     ddr_rasb;             
output     ddr_casb;             
output     ddr_web;              
output     [((`mask_width/2)-1):0]  ddr_dm;           
output     [`bank_address-1:0]ddr_ba;           
output     [`row_address-1:0]ddr_address;     
output     ddr1_clk0;             
output     ddr1_clk0b;            
output     ddr1_clk1;             
output     ddr1_clk1b;            

wire rst_calib;     
wire [4:0]delay_sel;
wire sys_rst;       
wire sys_rst90;     
wire sys_rst180;    
wire sys_rst270;    
wire clk_int;       
wire clk90_int;     

wire write_enable;      
wire dqs_div_rst;       
wire dqs_enable;        
wire dqs_reset;         
wire dqs_int_delay_in0; 
wire dqs_int_delay_in1; 
wire dqs_int_delay_in2; 
wire [23:0]dq; 
wire u_data_val;    

wire write_en_val; 
wire reset90_r;    
wire [((`mask_width/2)-1):0] data_mask_f;  
wire [((`mask_width/2)-1):0] data_mask_r;  
wire [23:0]write_data_falling;
wire [23:0]write_data_rising; 

wire ddr_rasb_cntrl; 
wire ddr_casb_cntrl; 
wire ddr_web_cntrl;  
wire [`bank_address-1:0]ddr_ba_cntrl;
wire [`row_address-1:0]ddr_address_cntrl;
wire ddr_cke_cntrl;    
wire ddr_csb_cntrl;    
wire rst_dqs_div_int;  




 controller1_24bit controller0  (
.auto_ref_req      (auto_ref_req), 
.wait_200us(wait_200us), 
                                   .dip1              ( dip1),
                                   .dip3              ( dip3),
	 .clk               (clk_int), 
//XST_REMOVECOMMENT  .clk180 (clk180),
                                   .rst0              (sys_rst),
                                   .rst180            (sys_rst180),
                                   .address           (user_input_address),
                                    .bank_address      (user_bank_address),
                                   .config_register   (user_config_register),
                                   .command_register  (user_command_register),
                                   .burst_done        (burst_done),
                                   .ddr_rasb_cntrl    (ddr_rasb_cntrl),
                                   .ddr_casb_cntrl    (ddr_casb_cntrl),
                                   .ddr_web_cntrl     (ddr_web_cntrl),
                                   .ddr_ba_cntrl      (ddr_ba_cntrl),
                                   .ddr_address_cntrl (ddr_address_cntrl),
                                   .ddr_cke_cntrl     (ddr_cke_cntrl),
                                   .ddr_csb_cntrl     (ddr_csb_cntrl),
                                   .dqs_enable        (dqs_enable),
                                   .dqs_reset         (dqs_reset),
                                   .write_enable      (write_enable),
                                   .rst_calib         (rst_calib),
                                   .rst_dqs_div_int   (rst_dqs_div_int),
                                   .cmd_ack           (user_cmd_ack),
                                   .init              (init_val),
                                   .ar_done           (ar_done)
                                   
                                  );
                             
data_path_24bit	data_path0	( 
                                 .user_input_data    (user_input_data),
					   .user_data_mask    (user_data_mask),	
 	 .clk               (clk_int), 
	 .clk90            (clk90_int), 
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
                                 .reset              (sys_rst),
                                 .reset90            (sys_rst90),
                                 .reset180           (sys_rst180),
                                 .reset270           (sys_rst270),
                                 .write_enable       (write_enable),
                                 .rst_dqs_div_in        (dqs_div_rst),
                                .delay_sel          (delay_sel),
                                 .dqs_int_delay_in0  (dqs_int_delay_in0),
                                 .dqs_int_delay_in1  (dqs_int_delay_in1),
                                 .dqs_int_delay_in2  (dqs_int_delay_in2),
                                .dq                 (dq),      
                                 .u_data_val         (user_data_valid),
                                 .user_output_data   (user_output_data),
                                 .write_en_val       (write_en_val),
                                 .reset90_r_val     (reset90_r),
                                 .data_mask_f        (data_mask_f),
                                 .data_mask_r        (data_mask_r),
                                 .write_data_falling (write_data_falling),
                                 .write_data_rising  (write_data_rising)                     
                                );                           
                          		
							
infrastructure infrastructure0 
(
                                         .sys_rst(sys_rst),
                                         .clk_int(clk_int),
                                         .rst_calib1(rst_calib),
                                         .delay_sel_val(delay_sel_val),
                                         .delay_sel_val1_val(delay_sel)
                                          );
iobs1_24bit	iobs0 
                    (
	 .clk               (clk_int), 
	 .clk90            (clk90_int), 
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
                     .ddr_rasb_cntrl    (ddr_rasb_cntrl), 
                     .ddr_casb_cntrl    (ddr_casb_cntrl),
                     .ddr_web_cntrl     (ddr_web_cntrl),
                     .ddr_cke_cntrl     (ddr_cke_cntrl),
                     .ddr_csb_cntrl     (ddr_csb_cntrl),
                     .ddr_address_cntrl (ddr_address_cntrl),
                     .ddr_ba_cntrl      (ddr_ba_cntrl),
                     .rst_dqs_div_int   (rst_dqs_div_int),
                     .dqs_reset         (dqs_reset),
                     .dqs_enable        (dqs_enable),
                     .ddr_dqs           (ddr_dqs),
                     .ddr_dq            (ddr_dq),
                     .write_data_falling(write_data_falling), 
                     .write_data_rising (write_data_rising),
                     .write_en_val      (write_en_val),
                     .reset90_r        (reset90_r),
                     .data_mask_f       (data_mask_f), 
                     .data_mask_r       (data_mask_r),
                     .ddr1_clk0         (ddr1_clk0), 
                     .ddr1_clk0b        (ddr1_clk0b),
                     .ddr1_clk1         (ddr1_clk1),
                     .ddr1_clk1b        (ddr1_clk1b),
                     .ddr_rasb          (ddr_rasb), 
                     .ddr_casb          (ddr_casb),
                     .ddr_web           (ddr_web),
                     .ddr_ba            (ddr_ba),
                     .ddr_address       (ddr_address),
                     .ddr_cke           (ddr_cke),
                     .ddr_csb           (ddr_csb),
                     .rst_dqs_div       (dqs_div_rst),
                     .rst_dqs_div_in	   (rst_dqs_div_in),
		         .rst_dqs_div_out	  ( rst_dqs_div_out),
                     .dqs_int_delay_in0 (dqs_int_delay_in0),
                     .dqs_int_delay_in1 (dqs_int_delay_in1),
                     .dqs_int_delay_in2 (dqs_int_delay_in2),
                     .dq                (dq),
                     .ddr_dm            (ddr_dm)
                    );							

endmodule