iobs_24bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

`include "parameters_24bit.v"
`timescale 1ns/100ps
module    iobs1_24bit   ( 

     clk,     
     clk90,   
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,   
     ddr_rasb_cntrl,   
     ddr_casb_cntrl,   
     ddr_web_cntrl,    
     ddr_cke_cntrl,    
     ddr_csb_cntrl,    
     ddr_address_cntrl,
     ddr_ba_cntrl,     
     rst_dqs_div_int,  
     dqs_reset,        
     dqs_enable,       
     ddr_dqs,          
     ddr_dq,           
     write_data_falling,
     write_data_rising,
     write_en_val,     
     reset90_r,        
     data_mask_f,      
     data_mask_r,      
     ddr1_clk0,        
     ddr1_clk0b,       
     ddr1_clk1,        
     ddr1_clk1b,       
     ddr_rasb,         
     ddr_casb,         
     ddr_web,         
     ddr_ba,          
     ddr_address,     
     ddr_cke,         
     ddr_csb,         
     rst_dqs_div,     
     rst_dqs_div_in,   
     rst_dqs_div_out,  
     dqs_int_delay_in0, 
     dqs_int_delay_in1, 
     dqs_int_delay_in2, 
     dq,                
     ddr_dm           
);

input     clk;               
input     clk90;             
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;   
input     ddr_rasb_cntrl;    
input     ddr_casb_cntrl;    
input     ddr_web_cntrl;     
input     ddr_cke_cntrl;     
input     ddr_csb_cntrl;     
input     [`row_address-1:0]ddr_address_cntrl; 
input     [`bank_address-1:0]ddr_ba_cntrl;    
input     rst_dqs_div_int;   
input     dqs_reset;         
input     dqs_enable;        
inout     [2:0]ddr_dqs;      
inout     [23:0]ddr_dq;      
input     [23:0]write_data_falling;
input     [23:0]write_data_rising;
input     write_en_val;      
input     reset90_r;        
input     [2:0]data_mask_f;
input     [2:0]data_mask_r; 
output     ddr1_clk0;       
output     ddr1_clk0b;      
output     ddr1_clk1;       
output     ddr1_clk1b;      
output     ddr_rasb;          
output     ddr_casb;         
output     ddr_web;          
output     [`bank_address-1:0]ddr_ba;      
output     [`row_address-1:0]ddr_address;
output     ddr_cke;          
output     ddr_csb;          
output     rst_dqs_div;      
input	   rst_dqs_div_in;  
output     rst_dqs_div_out;
output     dqs_int_delay_in0;  
output     dqs_int_delay_in1; 
output     dqs_int_delay_in2; 
output     [23:0]dq;           
output     [((`mask_width/2)-1):0]ddr_dm; 
       

infrastructure_iobs_24bit    infrastructure_iobs0   ( 
                                                     .clk0             (clk),
                                                     .clk90            (clk90),
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
                                                     .ddr1_clk0        (ddr1_clk0),
                                                     .ddr1_clk0b       (ddr1_clk0b),
                                                     .ddr1_clk1        (ddr1_clk1),
                                                     .ddr1_clk1b       (ddr1_clk1b)
                                                    );

controlle1_iobs    controller_iobs0   ( 
                                             .clk0              (clk),
//XST_REMOVECOMMENT  .clk180 (clk180),
                                             .ddr_rasb_cntrl    (ddr_rasb_cntrl),
                                             .ddr_casb_cntrl    (ddr_casb_cntrl),
                                             .ddr_web_cntrl     (ddr_web_cntrl), 
                                             .ddr_cke_cntrl     (ddr_cke_cntrl),
                                             .ddr_csb_cntrl     (ddr_csb_cntrl),
                                             .ddr_address_cntrl (ddr_address_cntrl),
                                             .ddr_ba_cntrl      (ddr_ba_cntrl),
                                             .rst_dqs_div_int   (rst_dqs_div_int),
                                             .ddr_rasb          (ddr_rasb),
                                             .ddr_casb          (ddr_casb),
                                             .ddr_web           (ddr_web),
                                             .ddr_ba            (ddr_ba),
                                             .ddr_address       (ddr_address),
                                             .ddr_cke           (ddr_cke),
                                             .ddr_csb           (ddr_csb), 
                                             .rst_dqs_div       (rst_dqs_div),
                                           		.rst_dqs_div_in	   (rst_dqs_div_in),
                   		                        .rst_dqs_div_out	  (rst_dqs_div_out)
                   		               );         	
											                                            

data_path_iobs_24bit    datapath_iobs0   ( 
                                         .clk                (clk),
				         .clk90              (clk90),
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
				         .reset90_r          (reset90_r),
                                         .dqs_reset          (dqs_reset),
                                         .dqs_enable         (dqs_enable),
                                         .ddr_dqs            (ddr_dqs),
                                         .ddr_dq             (ddr_dq),
                                         .write_data_falling (write_data_falling),
                                         .write_data_rising  (write_data_rising),
                                         .write_en_val       (write_en_val),
                                         .data_mask_f        (data_mask_f),
                                         .data_mask_r        (data_mask_r),
                                         .dqs_int_delay_in0  (dqs_int_delay_in0),
                                         .dqs_int_delay_in1  (dqs_int_delay_in1),
                                         .dqs_int_delay_in2  (dqs_int_delay_in2),
                                         .ddr_dq_val         (dq), 
                                         .ddr_dm             (ddr_dm)
                                        );

   
endmodule