infrastructure_iobs_24bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module    infrastructure_iobs_24bit   ( 

      clk0,              
      clk90,             
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
      ddr1_clk0,         
      ddr1_clk0b,        
      ddr1_clk1,         
      ddr1_clk1b,        
      ddr1_clk2,         
      ddr1_clk2b,        
      ddr1_clk3,         
      ddr1_clk3b,        
      ddr1_clk4,         
      ddr1_clk4b,        
      ddr1_clk5,         
      ddr1_clk5b        
      );
      
input      clk0;              
input      clk90;             
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
output      ddr1_clk0;         
output      ddr1_clk0b;        
output      ddr1_clk1;         
output      ddr1_clk1b;        
output      ddr1_clk2;         
output      ddr1_clk2b;        
output      ddr1_clk3;         
output      ddr1_clk3b;        
output      ddr1_clk4;         
output      ddr1_clk4b;        
output      ddr1_clk5;         
output      ddr1_clk5b;        
   
wire ddr1_clk0_q; 
wire ddr1_clk0b_q;
wire ddr1_clk1_q; 
wire ddr1_clk1b_q;
wire ddr1_clk2_q; 
wire ddr1_clk2b_q;
wire ddr1_clk3_q; 
wire ddr1_clk3b_q;
wire ddr1_clk4_q; 
wire ddr1_clk4b_q;
wire ddr1_clk5_q;          
wire ddr1_clk5b_q;         

wire vcc;   
wire gnd;   
//SYN_REMOVECOMMENT wire clk180;
//SYN_REMOVECOMMENT wire clk270;
   
   
//SYN_REMOVECOMMENT assign clk180 = ~ clk0;
//SYN_REMOVECOMMENT assign  clk270 = ~ clk90;
assign  gnd = 1'b0;
assign  vcc = 1'b1;   





//----  Component instantiations  ----

//--- ***********************************
//---  DCI Input buffer for System clock

//---- ***********************************************************
//----     Output DDR generation
//----     This includes instantiation of the output DDR flip flop
//----     for ddr clk's 
//---- ***********************************************************


FDDRRSE DDRCLK0_INST    ( .Q  (ddr1_clk0_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK0B_INST    ( .Q  (ddr1_clk0b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
                                   
FDDRRSE DDRCLK1_INST    ( .Q  (ddr1_clk1_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK1B_INST    ( .Q  (ddr1_clk1b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK2_INST    ( .Q  (ddr1_clk2_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK2B_INST    ( .Q  (ddr1_clk2b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );


FDDRRSE DDRCLK3_INST    ( .Q  (ddr1_clk3_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK3B_INST    ( .Q  (ddr1_clk3b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK4_INST    ( .Q  (ddr1_clk4_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK4B_INST    ( .Q  (ddr1_clk4b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK5_INST    ( .Q  (ddr1_clk5_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK5B_INST    ( .Q  (ddr1_clk5b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   

//---- ******************************************
//---- Ouput BUffers for ddr clk's and dimm clk's
//---- ******************************************


OBUF r1  ( .I(ddr1_clk0_q),  .O(ddr1_clk0));

OBUF r2  ( .I(ddr1_clk0b_q),  .O(ddr1_clk0b));

OBUF r3  ( .I(ddr1_clk1_q),  .O(ddr1_clk1));

OBUF r4  ( .I(ddr1_clk1b_q),  .O(ddr1_clk1b));

OBUF r5  ( .I(ddr1_clk2_q),  .O(ddr1_clk2));

OBUF r6  ( .I(ddr1_clk2b_q),  .O(ddr1_clk2b));

OBUF r7  ( .I(ddr1_clk3_q),  .O(ddr1_clk3));

OBUF r8  ( .I(ddr1_clk3b_q),  .O(ddr1_clk3b));

OBUF r9  ( .I(ddr1_clk4_q),  .O(ddr1_clk4));

OBUF r10  ( .I(ddr1_clk4b_q),  .O(ddr1_clk4b));

OBUF r17  ( .I(ddr1_clk5_q),  .O(ddr1_clk5));

OBUF r18  ( .I(ddr1_clk5b_q),  .O(ddr1_clk5b));


endmodule