iobs.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
`include "parameters_24bit.v" 
module iobs (

     SYS_CLK,
     SYS_CLKb,
     clk,     
     clk90,   
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,   
     rst_dqs_div_int,  
     dqs_reset,        
     dqs_enable,       
     ddr_dqs,          
     ddr_dq,           
     write_data_falling,
     write_data_rising,
     write_en_val,     
     reset90_r,        
     data_mask_f,      
     data_mask_r,      
     sys_clk_ibuf,     
     rst_dqs_div,     
     rst_dqs_div_in,   
     rst_dqs_div_out,  
     dqs_int_delay_in0, 
     dqs_int_delay_in1, 
     dqs_int_delay_in2, 
     dq,                
     ddr_dm           
);

input     SYS_CLK;           
input     SYS_CLKb;          
input     clk;               
input     clk90;             
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;   
input     rst_dqs_div_int;   
input     dqs_reset;         
input     dqs_enable;        
inout     [2:0]ddr_dqs;      
inout     [23:0]ddr_dq;      
input     [23:0]write_data_falling;
input     [23:0]write_data_rising;
input     write_en_val;      
input     reset90_r;        
input     [2:0]data_mask_f;
input     [2:0]data_mask_r; 
output     sys_clk_ibuf;    
output     rst_dqs_div;      
input	   rst_dqs_div_in;  
output     rst_dqs_div_out;
output     dqs_int_delay_in0;  
output     dqs_int_delay_in1; 
output     dqs_int_delay_in2; 
output     [23:0]dq;           
output     [2:0]ddr_dm; 
       

infrastructure_iobs infrastructure_iobs0   (
                                                     .SYS_CLK          (SYS_CLK),
                                                     .SYS_CLKb         (SYS_CLKb),
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
                                                     .rst_dqs_div_int  (rst_dqs_div_int),
                                                     .rst_dqs_div_in   (rst_dqs_div_in),
                                                     .rst_dqs_div      (rst_dqs_div),
                                                     .rst_dqs_div_out  (rst_dqs_div_out),
                                                     .sys_clk_ibuf     (sys_clk_ibuf)
                                                    );


 data_path_iobs_24bit datapath_iobs0  (
                                         .clk                (clk),
				         .clk90              (clk90),
//XST_REMOVECOMMENT  .clk180 (clk180),
//XST_REMOVECOMMENT  .clk270 (clk270),
				         .reset90_r          (reset90_r),
                                         .dqs_reset          (dqs_reset),
                                         .dqs_enable         (dqs_enable),
                                         .ddr_dqs            (ddr_dqs),
                                         .ddr_dq             (ddr_dq),
                                         .write_data_falling (write_data_falling),
                                         .write_data_rising  (write_data_rising),
                                         .write_en_val       (write_en_val),
                                         .data_mask_f        (data_mask_f),
                                         .data_mask_r        (data_mask_r),
                                         .dqs_int_delay_in0  (dqs_int_delay_in0),
                                         .dqs_int_delay_in1  (dqs_int_delay_in1),
                                         .dqs_int_delay_in2  (dqs_int_delay_in2),
                                         .ddr_dq_val         (dq),
                                         .ddr_dm             (ddr_dm)
                                        );

   
endmodule