📄 data_read_24bit.v
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RAM16X1D fifo1_bit4 (.DPO (fifo_01_data_out[4]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[4]),
.DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]),
.DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
.WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));
RAM16X1D fifo0_bit5 (.DPO (fifo_00_data_out[5]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[5]),
.DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]),
.DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
.WCLK(dqs0_delayed_col0), .WE(fifo_00_wr_en));
RAM16X1D fifo1_bit5 (.DPO (fifo_01_data_out[5]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[5]),
.DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]),
.DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
.WCLK(dqs0_delayed_col0_n), .WE(fifo_01_wr_en));
RAM16X1D fifo0_bit6 (.DPO (fifo_00_data_out[6]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[6]),
.DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]),
.DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
.WCLK(dqs0_delayed_col1), .WE(fifo_00_wr_en));
RAM16X1D fifo1_bit6 (.DPO (fifo_01_data_out[6]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[6]),
.DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]),
.DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
.WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));
RAM16X1D fifo0_bit7 (.DPO (fifo_00_data_out[7]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[7]),
.DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]),
.DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
.WCLK(dqs0_delayed_col0), .WE(fifo_00_wr_en));
RAM16X1D fifo1_bit7 (.DPO (fifo_01_data_out[7]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[7]),
.DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]),
.DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
.WCLK(dqs0_delayed_col0_n), .WE(fifo_01_wr_en));
RAM16X1D fifo0_bit8 (.DPO (fifo_10_data_out[0]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[8]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit8 (.DPO (fifo_11_data_out[0]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[8]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit9 (.DPO (fifo_10_data_out[1]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[9]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit9 (.DPO (fifo_11_data_out[1]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[9]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit10 (.DPO (fifo_10_data_out[2]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[10]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit10 (.DPO (fifo_11_data_out[2]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[10]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit11 (.DPO (fifo_10_data_out[3]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[11]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit11 (.DPO (fifo_11_data_out[3]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[11]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit12 (.DPO (fifo_10_data_out[4]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[12]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit12 (.DPO (fifo_11_data_out[4]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[12]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit13 (.DPO (fifo_10_data_out[5]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[13]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit13 (.DPO (fifo_11_data_out[5]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[13]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit14 (.DPO (fifo_10_data_out[6]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[14]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit14 (.DPO (fifo_11_data_out[6]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[14]),
.DPRA0(fifo10_rd_addr_r[0]), .DPRA1(fifo10_rd_addr_r[1]),
.DPRA2(fifo10_rd_addr_r[2]), .DPRA3(fifo10_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col1_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit15 (.DPO (fifo_10_data_out[7]), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(ddr_dq_in[15]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0), .WE(fifo_10_wr_en));
RAM16X1D fifo1_bit15 (.DPO (fifo_11_data_out[7]), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(ddr_dq_in[15]),
.DPRA0(fifo11_rd_addr_r[0]), .DPRA1(fifo11_rd_addr_r[1]),
.DPRA2(fifo11_rd_addr_r[2]), .DPRA3(fifo11_rd_addr_r[3]), .SPO(),
.WCLK(dqs1_delayed_col0_n), .WE(fifo_11_wr_en));
RAM16X1D fifo0_bit16 (.DPO (fifo_20_data_out[0]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[16]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit16 (.DPO (fifo_21_data_out[0]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[16]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit17 (.DPO (fifo_20_data_out[1]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[17]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit17 (.DPO (fifo_21_data_out[1]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[17]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit18 (.DPO (fifo_20_data_out[2]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[18]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit18 (.DPO (fifo_21_data_out[2]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[18]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit19 (.DPO (fifo_20_data_out[3]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[19]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit19 (.DPO (fifo_21_data_out[3]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[19]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit20 (.DPO (fifo_20_data_out[4]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[20]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit20 (.DPO (fifo_21_data_out[4]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[20]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit21 (.DPO (fifo_20_data_out[5]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[21]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit21 (.DPO (fifo_21_data_out[5]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[21]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit22 (.DPO (fifo_20_data_out[6]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[22]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit22 (.DPO (fifo_21_data_out[6]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[22]),
.DPRA0(fifo20_rd_addr_r[0]), .DPRA1(fifo20_rd_addr_r[1]),
.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit23 (.DPO (fifo_20_data_out[7]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[23]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit23 (.DPO (fifo_21_data_out[7]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[23]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0_n), .WE(fifo_21_wr_en));
endmodule
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