data_path_iobs_24bit.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 423 行 · 第 1/2 页

      				.write_data_rising  (write_data_rising[6]),
      				.read_data_in       (ddr_dq_in[6]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
 ddr_dq_iob  ddr_dq_iob7 
				(
      				.ddr_dq_inout       (ddr_dq[7]), 
      				.write_data_falling (write_data_falling[7]), 
      				.write_data_rising  (write_data_rising[7]),
      				.read_data_in       (ddr_dq_in[7]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob8 
				(
      				.ddr_dq_inout       (ddr_dq[8]), 
      				.write_data_falling (write_data_falling[8]), 
      				.write_data_rising  (write_data_rising[8]),
      				.read_data_in       (ddr_dq_in[8]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob9 
				(
      				.ddr_dq_inout       (ddr_dq[9]), 
      				.write_data_falling (write_data_falling[9]), 
      				.write_data_rising  (write_data_rising[9]),
      				.read_data_in       (ddr_dq_in[9]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );

 ddr_dq_iob  ddr_dq_iob10 
				(
      				.ddr_dq_inout       (ddr_dq[10]), 
      				.write_data_falling (write_data_falling[10]), 
      				.write_data_rising  (write_data_rising[10]),
      				.read_data_in       (ddr_dq_in[10]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob11 
				(
      				.ddr_dq_inout       (ddr_dq[11]), 
      				.write_data_falling (write_data_falling[11]), 
      				.write_data_rising  (write_data_rising[11]),
      				.read_data_in       (ddr_dq_in[11]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob12 
				(
      				.ddr_dq_inout       (ddr_dq[12]), 
      				.write_data_falling (write_data_falling[12]), 
      				.write_data_rising  (write_data_rising[12]),
      				.read_data_in       (ddr_dq_in[12]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob13 
				(
      				.ddr_dq_inout       (ddr_dq[13]), 
      				.write_data_falling (write_data_falling[13]), 
      				.write_data_rising  (write_data_rising[13]),
      				.read_data_in       (ddr_dq_in[13]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob14 
				(
      				.ddr_dq_inout       (ddr_dq[14]), 
      				.write_data_falling (write_data_falling[14]), 
      				.write_data_rising  (write_data_rising[14]),
      				.read_data_in       (ddr_dq_in[14]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
  
 ddr_dq_iob  ddr_dq_iob15 
				(
      				.ddr_dq_inout       (ddr_dq[15]), 
      				.write_data_falling (write_data_falling[15]), 
      				.write_data_rising  (write_data_rising[15]),
      				.read_data_in       (ddr_dq_in[15]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob16 
				(
      				.ddr_dq_inout       (ddr_dq[16]), 
      				.write_data_falling (write_data_falling[16]), 
      				.write_data_rising  (write_data_rising[16]),
      				.read_data_in       (ddr_dq_in[16]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
 ddr_dq_iob  ddr_dq_iob17 
				(
      				.ddr_dq_inout       (ddr_dq[17]), 
      				.write_data_falling (write_data_falling[17]), 
      				.write_data_rising  (write_data_rising[17]),
      				.read_data_in       (ddr_dq_in[17]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob18 
				(
      				.ddr_dq_inout       (ddr_dq[18]), 
      				.write_data_falling (write_data_falling[18]), 
      				.write_data_rising  (write_data_rising[18]),
      				.read_data_in       (ddr_dq_in[18]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob19 
				(
      				.ddr_dq_inout       (ddr_dq[19]), 
      				.write_data_falling (write_data_falling[19]), 
      				.write_data_rising  (write_data_rising[19]),
      				.read_data_in       (ddr_dq_in[19]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
 ddr_dq_iob  ddr_dq_iob20 
				(
      				.ddr_dq_inout       (ddr_dq[20]), 
      				.write_data_falling (write_data_falling[20]), 
      				.write_data_rising  (write_data_rising[20]),
      				.read_data_in       (ddr_dq_in[20]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob21 
				(
      				.ddr_dq_inout       (ddr_dq[21]), 
      				.write_data_falling (write_data_falling[21]), 
      				.write_data_rising  (write_data_rising[21]),
      				.read_data_in       (ddr_dq_in[21]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob22 
				(
      				.ddr_dq_inout       (ddr_dq[22]), 
      				.write_data_falling (write_data_falling[22]), 
      				.write_data_rising  (write_data_rising[22]),
      				.read_data_in       (ddr_dq_in[22]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob23 
				(
      				.ddr_dq_inout       (ddr_dq[23]), 
      				.write_data_falling (write_data_falling[23]), 
      				.write_data_rising  (write_data_rising[23]),
      				.read_data_in       (ddr_dq_in[23]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     

endmodule