data_read_16bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module    data_read_16bit   ( 

     clk,               
     clk90,             
     reset90_r,         
     reset270_r,        
     ddr_dq_in,         
     read_valid_data_1,  
     fifo_00_wr_en,			
     fifo_10_wr_en,			
     fifo_20_wr_en,			
     fifo_30_wr_en,			
     			
     fifo_01_wr_en,			
     fifo_11_wr_en,			
     fifo_21_wr_en,			
     fifo_31_wr_en,			
     		
     fifo_00_wr_addr,    
     fifo_01_wr_addr,    
     fifo_10_wr_addr,    
     fifo_11_wr_addr,    
     fifo_20_wr_addr,    
     fifo_21_wr_addr,    
     fifo_30_wr_addr,    
     fifo_31_wr_addr,    

     dqs0_delayed_col1,  
     dqs1_delayed_col1,  
     dqs2_delayed_col1,  
     dqs3_delayed_col1,  
     
     dqs0_delayed_col0_n,
     dqs1_delayed_col0_n,
     dqs2_delayed_col0_n,
     dqs3_delayed_col0_n,

     user_output_data,

     fifo_00_rd_addr,
     fifo_01_rd_addr,
     fifo_10_rd_addr,
     fifo_11_rd_addr,
     fifo_20_rd_addr,
     fifo_21_rd_addr,
     fifo_30_rd_addr,
     fifo_31_rd_addr
);

 

input     clk;       
input     clk90;     
input     reset90_r; 
input     reset270_r;

input     [15:0]ddr_dq_in;
input     read_valid_data_1;
     
input     fifo_00_wr_en;
input     fifo_10_wr_en;
input     fifo_20_wr_en;			
input     fifo_30_wr_en;			

input     fifo_01_wr_en;			
input     fifo_11_wr_en;			
input     fifo_21_wr_en;			
input     fifo_31_wr_en;			
		
input     [3:0]fifo_00_wr_addr; 
input     [3:0]fifo_01_wr_addr; 
input     [3:0]fifo_10_wr_addr; 
input     [3:0]fifo_11_wr_addr; 
input     [3:0]fifo_20_wr_addr; 
input     [3:0]fifo_21_wr_addr; 
input     [3:0]fifo_30_wr_addr; 
input     [3:0]fifo_31_wr_addr; 
		
input     dqs0_delayed_col1;  
input     dqs1_delayed_col1;  
input     dqs2_delayed_col1;  
input     dqs3_delayed_col1;  
     
input     dqs0_delayed_col0_n;
input     dqs1_delayed_col0_n;
input     dqs2_delayed_col0_n;
input     dqs3_delayed_col0_n;
     
output     [31:0]user_output_data; 

input     [3:0]fifo_00_rd_addr;
input     [3:0]fifo_01_rd_addr;
input     [3:0]fifo_10_rd_addr;
input     [3:0]fifo_11_rd_addr;
input     [3:0]fifo_20_rd_addr;
input     [3:0]fifo_21_rd_addr;
input     [3:0]fifo_30_rd_addr;
input     [3:0]fifo_31_rd_addr;

wire [3:0]fifo_00_data_out;
wire [3:0]fifo_01_data_out;
wire [3:0]fifo_10_data_out;
wire [3:0]fifo_11_data_out;
wire [3:0]fifo_20_data_out;
wire [3:0]fifo_21_data_out;
wire [3:0]fifo_30_data_out;
wire [3:0]fifo_31_data_out;

reg [31:0]first_sdr_data; 


assign user_output_data    = first_sdr_data;

always@(posedge clk90)
begin
    if (reset90_r == 1'b1)
    	first_sdr_data   <= 32'b0;
    else
    begin
             if (read_valid_data_1 == 1'b1)
               first_sdr_data  <= {
               				   fifo_30_data_out,fifo_20_data_out,
               				   fifo_10_data_out,fifo_00_data_out,
               				   fifo_31_data_out,fifo_21_data_out,
               				   fifo_11_data_out,fifo_01_data_out};
             else
               first_sdr_data  <= first_sdr_data;               
     end
end     

//*************************************************************************************************************************
// Dual Port RAM 16x1 instantiations (fifo0 // Positive edge, fifo1 -- Trailing edge) 
//*************************************************************************************************************************
// NOTE the change in fifo_00_data_out etc buffers size. Its now changed to 3:0  from 7:0.
//- Nibble0 instantiation


 RAM16X1D fifo0_bit0               
	 (.DPO(fifo_00_data_out[0]), 
	  .SPO( ),       
          .A0(fifo_00_wr_addr[0]),          
          .A1(fifo_00_wr_addr[1]),
          .A2(fifo_00_wr_addr[2]),
          .A3(fifo_00_wr_addr[3]),
          .D(ddr_dq_in[0]),      
          .DPRA0(fifo_00_rd_addr[0]),
          .DPRA1(fifo_00_rd_addr[1]),
          .DPRA2(fifo_00_rd_addr[2]),
          .DPRA3(fifo_00_rd_addr[3]),
          .WCLK(dqs0_delayed_col1),          
          .WE(fifo_00_wr_en)
           );                       

 RAM16X1D fifo1_bit0               
	 ( .DPO(fifo_01_data_out[0]),
	   .SPO( ),          
          .A0(fifo_01_wr_addr[0]),          
          .A1(fifo_01_wr_addr[1]),
          .A2(fifo_01_wr_addr[2]),
          .A3(fifo_01_wr_addr[3]),
          .D(ddr_dq_in[0]),      
          .DPRA0(fifo_01_rd_addr[0]),
          .DPRA1(fifo_01_rd_addr[1]),
          .DPRA2(fifo_01_rd_addr[2]),
          .DPRA3(fifo_01_rd_addr[3]),
          .WCLK(dqs0_delayed_col0_n),          
          .WE(fifo_01_wr_en)
           );                       

 RAM16X1D fifo0_bit1               
	 ( .DPO(fifo_00_data_out[1]),
	 .SPO( ),          
          .A0(fifo_00_wr_addr[0]),          
          .A1(fifo_00_wr_addr[1]),
          .A2(fifo_00_wr_addr[2]),
          .A3(fifo_00_wr_addr[3]),
          .D(ddr_dq_in[1]),      
          .DPRA0(fifo_00_rd_addr[0]),
          .DPRA1(fifo_00_rd_addr[1]),
          .DPRA2(fifo_00_rd_addr[2]),
          .DPRA3(fifo_00_rd_addr[3]),
          .WCLK(dqs0_delayed_col1),          
          .WE(fifo_00_wr_en)
           );                       

 RAM16X1D fifo1_bit1               
	 ( .DPO(fifo_01_data_out[1]),          
	 .SPO( ),
          .A0(fifo_01_wr_addr[0]),          
          .A1(fifo_01_wr_addr[1]),
          .A2(fifo_01_wr_addr[2]),
          .A3(fifo_01_wr_addr[3]),
          .D(ddr_dq_in[1]),      
          .DPRA0(fifo_01_rd_addr[0]),
          .DPRA1(fifo_01_rd_addr[1]),
          .DPRA2(fifo_01_rd_addr[2]),
          .DPRA3(fifo_01_rd_addr[3]),
          .WCLK(dqs0_delayed_col0_n),          
          .WE(fifo_01_wr_en)
           ); 
           
 RAM16X1D fifo0_bit2               
	 ( .DPO(fifo_00_data_out[2]),          
	 .SPO( ),
          .A0(fifo_00_wr_addr[0]),          
          .A1(fifo_00_wr_addr[1]),
          .A2(fifo_00_wr_addr[2]),
          .A3(fifo_00_wr_addr[3]),
          .D(ddr_dq_in[2]),      
          .DPRA0(fifo_00_rd_addr[0]),
          .DPRA1(fifo_00_rd_addr[1]),
          .DPRA2(fifo_00_rd_addr[2]),
          .DPRA3(fifo_00_rd_addr[3]),
          .WCLK(dqs0_delayed_col1),          
          .WE(fifo_00_wr_en)
           );                       

 RAM16X1D fifo1_bit2               
	 ( .DPO(fifo_01_data_out[2]),          
	 .SPO( ),
          .A0(fifo_01_wr_addr[0]),          
          .A1(fifo_01_wr_addr[1]),
          .A2(fifo_01_wr_addr[2]),
          .A3(fifo_01_wr_addr[3]),
          .D(ddr_dq_in[2]),      
          .DPRA0(fifo_01_rd_addr[0]),
          .DPRA1(fifo_01_rd_addr[1]),
          .DPRA2(fifo_01_rd_addr[2]),
          .DPRA3(fifo_01_rd_addr[3]),
          .WCLK(dqs0_delayed_col0_n),          
          .WE(fifo_01_wr_en)
           );                                  
            
 RAM16X1D fifo0_bit3               
	 ( .DPO(fifo_00_data_out[3]),          
	 .SPO( ),
          .A0(fifo_00_wr_addr[0]),          
          .A1(fifo_00_wr_addr[1]),
          .A2(fifo_00_wr_addr[2]),
          .A3(fifo_00_wr_addr[3]),
          .D(ddr_dq_in[3]),      
          .DPRA0(fifo_00_rd_addr[0]),
          .DPRA1(fifo_00_rd_addr[1]),
          .DPRA2(fifo_00_rd_addr[2]),
          .DPRA3(fifo_00_rd_addr[3]),
          .WCLK(dqs0_delayed_col1),          
          .WE(fifo_00_wr_en)
           );                       

 RAM16X1D fifo1_bit3               
	 ( .DPO(fifo_01_data_out[3]),          
	 .SPO( ),
          .A0(fifo_01_wr_addr[0]),          
          .A1(fifo_01_wr_addr[1]),
          .A2(fifo_01_wr_addr[2]),
          .A3(fifo_01_wr_addr[3]),
          .D(ddr_dq_in[3]),      
          .DPRA0(fifo_01_rd_addr[0]),
          .DPRA1(fifo_01_rd_addr[1]),
          .DPRA2(fifo_01_rd_addr[2]),
          .DPRA3(fifo_01_rd_addr[3]),
          .WCLK(dqs0_delayed_col0_n),          
          .WE(fifo_01_wr_en)
           );   
           
// Nibble1 instantiation            

 RAM16X1D fifo0_bit4               
	 ( .DPO(fifo_10_data_out[0]),          
	 .SPO( ),
          .A0(fifo_10_wr_addr[0]),          
          .A1(fifo_10_wr_addr[1]),
          .A2(fifo_10_wr_addr[2]),
          .A3(fifo_10_wr_addr[3]),
          .D(ddr_dq_in[4]),      
          .DPRA0(fifo_10_rd_addr[0]),
          .DPRA1(fifo_10_rd_addr[1]),
          .DPRA2(fifo_10_rd_addr[2]),
          .DPRA3(fifo_10_rd_addr[3]),
          .WCLK(dqs1_delayed_col1),          
          .WE(fifo_10_wr_en)
           );                       

 RAM16X1D fifo1_bit4               
	 ( .DPO(fifo_11_data_out[0]),          
	 .SPO( ),
          .A0(fifo_11_wr_addr[0]),          
          .A1(fifo_11_wr_addr[1]),
          .A2(fifo_11_wr_addr[2]),
          .A3(fifo_11_wr_addr[3]),
          .D(ddr_dq_in[4]),      
          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           );                                  
           
  RAM16X1D fifo0_bit5               
	 ( .DPO(fifo_10_data_out[1]),          
	 .SPO( ),
          .A0(fifo_10_wr_addr[0]),          
          .A1(fifo_10_wr_addr[1]),
          .A2(fifo_10_wr_addr[2]),
          .A3(fifo_10_wr_addr[3]),
          .D(ddr_dq_in[5]),      
          .DPRA0(fifo_10_rd_addr[0]),
          .DPRA1(fifo_10_rd_addr[1]),
          .DPRA2(fifo_10_rd_addr[2]),
          .DPRA3(fifo_10_rd_addr[3]),
          .WCLK(dqs1_delayed_col1),          
          .WE(fifo_10_wr_en)
           );                       

 RAM16X1D fifo1_bit5               
	 ( .DPO(fifo_11_data_out[1]),          
	 .SPO( ),
          .A0(fifo_11_wr_addr[0]),          
          .A1(fifo_11_wr_addr[1]),
          .A2(fifo_11_wr_addr[2]),
          .A3(fifo_11_wr_addr[3]),
          .D(ddr_dq_in[5]),      
          .DPRA0(fifo_11_rd_addr[0]),
          .DPRA1(fifo_11_rd_addr[1]),
          .DPRA2(fifo_11_rd_addr[2]),
          .DPRA3(fifo_11_rd_addr[3]),
          .WCLK(dqs1_delayed_col0_n),          
          .WE(fifo_11_wr_en)
           );