infrastructure_iobs.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 50 行

  `timescale 1ns/100ps
module infrastructure_iobs (

      SYS_CLK,           
      SYS_CLKb,
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
      rst_dqs_div_int,
      rst_dqs_div_in,
      rst_dqs_div,
      rst_dqs_div_out,          
      sys_clk_ibuf
      );
      
input      SYS_CLK;           
input      SYS_CLKb; 
//XST_REMOVECOMMENT input     clk180;
//XST_REMOVECOMMENT input     clk270;
input      rst_dqs_div_int; 
input	   rst_dqs_div_in; 
output     rst_dqs_div;     
output	   rst_dqs_div_out;         
output     sys_clk_ibuf;      
   

//--- ***********************************
//---  DCI Input buffer for System clock
//---   
//--- ***********************************

IBUFGDS_LVDS_25 lvds_clk_input   ( 
                                           .I  (SYS_CLK),      
                                           .IB (SYS_CLKb),     
                                           .O  (sys_clk_ibuf)
                                           );


IBUF_SSTL2_II rst_iob_inbuf  
                            ( .I(rst_dqs_div_in),
                              .O(rst_dqs_div));
  

                            
OBUF_SSTL2_II rst_iob_outbuf  
                            ( .I(rst_dqs_div_int),
                              .O(rst_dqs_div_out));

endmodule