📄 data_read_controller_16bit.v
字号:
//*********************************************************************
// DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins
// In the current DATA PATH logic DATA CAPTURE part was modified.
// The below changes were made to reduce the resources in
// the data capture
// in the current architecture data ( dq ) from ddr memory
// directly stored into the FIFO's.
// Architectural changes :
// Used only TWO FIFOs ( instead of FOUR FIFOs )
// Used Single col ( col0 ) dqs_delayed_col signals
// Used Gray Counters for write and read pointers of the FIFOs
// fbit stage is removed from ddr1_dqbit module ( in the data capture )
// dq_clk stage was removed
// dqs_clk_div logic was removed
// ddr1_transfer_done logic was removed
// data valid signals registering in clk90 domain was removed
// fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
// only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic
// write enable for the FIFOs derived from rst_dqs_div signal
// Code revised by : Narayana Murty.
// Date : Nov 18, 2003.
//*********************************************************************
`timescale 1ns/100ps
module data_read_controller_16bit (
clk,
clk90,
reset_r,
reset90_r,
reset180_r,
reset270_r,
rst_dqs_div_in,
delay_sel,
dqs_int_delay_in0,
dqs_int_delay_in1,
fifo_00_rd_addr_val,
fifo_01_rd_addr_val,
fifo_10_rd_addr_val,
fifo_11_rd_addr_val,
u_data_val,
read_valid_data_1_val,
fifo_00_wr_en_val,
fifo_10_wr_en_val,
fifo_01_wr_en_val,
fifo_11_wr_en_val,
fifo_00_wr_addr_val,
fifo_10_wr_addr_val,
fifo_01_wr_addr_val,
fifo_11_wr_addr_val,
dqs0_delayed_col0_val,
dqs1_delayed_col0_val,
dqs0_delayed_col0_n_val,
dqs1_delayed_col0_n_val
);
input clk;
input clk90;
input reset_r;
input reset90_r;
input reset180_r;
input reset270_r;
input rst_dqs_div_in;
input [4:0]delay_sel;
input dqs_int_delay_in0;
input dqs_int_delay_in1;
output [3:0]fifo_00_rd_addr_val;
output [3:0]fifo_01_rd_addr_val;
output [3:0]fifo_10_rd_addr_val;
output [3:0]fifo_11_rd_addr_val;
output u_data_val;
output read_valid_data_1_val;
output fifo_00_wr_en_val;
output fifo_10_wr_en_val;
output fifo_01_wr_en_val;
output fifo_11_wr_en_val;
output [3:0]fifo_00_wr_addr_val;
output [3:0]fifo_10_wr_addr_val;
output [3:0]fifo_01_wr_addr_val;
output [3:0]fifo_11_wr_addr_val;
output dqs0_delayed_col0_val;
output dqs1_delayed_col0_val;
output dqs0_delayed_col0_n_val;
output dqs1_delayed_col0_n_val;
reg u_data_val;
wire dqs_int_delay_in0;
wire dqs_int_delay_in1;
wire [1:0]dqs_delayed_col0;
wire resetn;
wire fifo_00_empty;
wire fifo_01_empty;
wire [3:0] fifo_00_wr_addr;
wire [3:0] fifo_10_wr_addr;
wire [3:0] fifo_01_wr_addr;
wire [3:0] fifo_11_wr_addr;
wire read_valid_data_0_1;
wire read_valid_data_1;
wire dqs0_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0 /* synthesis syn_keep=1 */;
wire dqs0_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0_n /* synthesis syn_keep=1 */;
wire TIE_HIGH;
// FIFO WRITE ENABLE SIGNALS
wire fifo_00_wr_en;
wire fifo_10_wr_en;
wire fifo_01_wr_en;
wire fifo_11_wr_en;
//signal rst_dqs_delay_n : std_logic;
wire rst_dqs_delay_0_n;
wire rst_dqs_delay_1_n;
wire rst_dqs_delay_2_n;
// FIFO_WR_POINTER Delayed signals in clk90 domain
wire [3:0]fifo_00_rd_addr;
wire [3:0]fifo_01_rd_addr;
wire [3:0]fifo_10_rd_addr;
wire [3:0]fifo_11_rd_addr;
reg [3:0]fifo_00_wr_addr_d;
reg [3:0]fifo_00_wr_addr_2d;
reg [3:0]fifo_01_wr_addr_d;
reg [3:0]fifo_01_wr_addr_2d;
assign fifo_00_wr_addr_val = fifo_00_wr_addr;
assign fifo_10_wr_addr_val = fifo_10_wr_addr;
assign fifo_01_wr_addr_val = fifo_01_wr_addr;
assign fifo_11_wr_addr_val = fifo_11_wr_addr;
assign fifo_00_wr_en_val = fifo_00_wr_en;
assign fifo_10_wr_en_val = fifo_10_wr_en;
assign fifo_01_wr_en_val = fifo_01_wr_en;
assign fifo_11_wr_en_val = fifo_11_wr_en;
assign dqs0_delayed_col0_n_val =dqs0_delayed_col0_n;
assign dqs1_delayed_col0_n_val =dqs1_delayed_col0_n;
assign dqs0_delayed_col0_val =dqs0_delayed_col0;
assign dqs1_delayed_col0_val =dqs1_delayed_col0;
///////////////////////////////////////////////////////////////////////////
assign dqs0_delayed_col0 = dqs_delayed_col0[0];
assign dqs1_delayed_col0 = dqs_delayed_col0[1];
assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
// TIE_HIGH assignment
assign TIE_HIGH = 1'b1;
assign resetn = ~ reset_r;
assign read_valid_data_0_1 = ( (~fifo_00_empty) && (~fifo_01_empty) );
assign read_valid_data_1_val = read_valid_data_0_1;
assign fifo_00_empty = (fifo_00_rd_addr[3:0] == fifo_00_wr_addr_2d[3:0] )? 1'b1 :1'b0;
assign fifo_01_empty = (fifo_01_rd_addr[3:0] == fifo_01_wr_addr_2d[3:0] )? 1'b1 :1'b0;
assign fifo_00_rd_addr_val=fifo_00_rd_addr;
assign fifo_01_rd_addr_val=fifo_01_rd_addr;
assign fifo_10_rd_addr_val=fifo_10_rd_addr;
assign fifo_11_rd_addr_val=fifo_11_rd_addr;
// FIFO WRITE POINTER DELAYED SIGNALS
// To avoid meta-stability due to the domain crossing from ddr_dqs to clk90
always@(posedge clk90)
begin
if (reset90_r == 1'b1)
begin
fifo_00_wr_addr_d <= 4'h0;
fifo_01_wr_addr_d <= 4'h0;
end
else
begin
fifo_00_wr_addr_d <= fifo_00_wr_addr;
fifo_01_wr_addr_d <= fifo_01_wr_addr;
end
end
// FIFO WRITE POINTER DOUBLE DELAYED SIGNALS
always@(posedge clk90)
begin
if (reset90_r == 1'b1)
begin
fifo_00_wr_addr_2d <= 4'h0;
fifo_01_wr_addr_2d <= 4'h0;
end
else
begin
fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
end
end
// user data valid output signal from data path.
always@(posedge clk90)
begin
if (reset90_r ==1'b1)
u_data_val <= 1'b0;
else
u_data_val <= read_valid_data_0_1;
end
dqs_delay rst_dqs_div_delayed (
.clk_in (rst_dqs_div_in),
.sel_in (delay_sel),
.clk_out (rst_dqs_div)
);
//**********************************************************************************************************
// fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
//**********************************************************************************************************
rd_gray_cntr fifo_00_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_00_rd_addr)
);
rd_gray_cntr fifo_01_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_01_rd_addr)
);
rd_gray_cntr fifo_10_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_10_rd_addr)
);
rd_gray_cntr fifo_11_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_11_rd_addr)
);
//**************************************************************************************************
// DQS Internal Delay Circuit implemented in LUTs
//**************************************************************************************************
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay0_col0 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[0])
);
dqs_delay dqs_delay1_col0 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[1])
);
//*************************************************************************************
// FIFO Write enable signal generation
//*************************************************************************************
fifo_0_wr_en fifo_00_wr_en_inst (
.clk (dqs0_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.dout (fifo_00_wr_en)
);
fifo_1_wr_en fifo_01_wr_en_inst (
.clk (dqs0_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_01_wr_en)
);
fifo_0_wr_en fifo_10_wr_en_inst (
.clk (dqs1_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.dout (fifo_10_wr_en)
);
fifo_1_wr_en fifo_11_wr_en_inst (
.clk (dqs1_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_11_wr_en)
);
//-------------------------------------------------------------------------------------------------
// write pointer gray counter instances
wr_gray_cntr fifo_00_wr_addr_inst (
.clk (dqs0_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_00_wr_en),
.wgc_gcnt (fifo_00_wr_addr)
);
wr_gray_cntr fifo_01_wr_addr_inst (
.clk (dqs0_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_01_wr_en),
.wgc_gcnt (fifo_01_wr_addr)
);
wr_gray_cntr fifo_10_wr_addr_inst (
.clk (dqs1_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_10_wr_en),
.wgc_gcnt (fifo_10_wr_addr)
);
wr_gray_cntr fifo_11_wr_addr_inst (
.clk (dqs1_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_11_wr_en),
.wgc_gcnt (fifo_11_wr_addr)
);
endmodule⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -