📄 data_read_controller_56bit.v
字号:
rd_gray_cntr fifo_131_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_131_rd_addr)
);
//-------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------------------------------------------------
//**************************************************************************************************
// DQS Internal Delay Circuit implemented in LUTs
//**************************************************************************************************
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay0_col0 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[0])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay0_col1 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[0])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay1_col0 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[1])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay1_col1 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[1])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay2_col0 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[2])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay2_col1 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[2])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay3_col0 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[3])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay3_col1 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[3])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay4_col0 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[4])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay4_col1 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[4])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay5_col0 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[5])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay5_col1 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[5])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay6_col0 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[6])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay6_col1 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[6])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay7_col0 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[7])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay7_col1 (
.clk_in(dqs_int_delay_in7),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[7])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay8_col0 (
.clk_in(dqs_int_delay_in8),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[8])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay8_col1 (
.clk_in(dqs_int_delay_in8),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[8])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay9_col0 (
.clk_in(dqs_int_delay_in9),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[9])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay9_col1 (
.clk_in(dqs_int_delay_in9),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[9])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay10_col0 (
.clk_in(dqs_int_delay_in10),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[10])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay10_col1 (
.clk_in(dqs_int_delay_in10),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[10])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay11_col0 (
.clk_in(dqs_int_delay_in11),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[11])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay11_col1 (
.clk_in(dqs_int_delay_in11),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[11])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay12_col0 (
.clk_in(dqs_int_delay_in12),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[12])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay12_col1 (
.clk_in(dqs_int_delay_in12),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[12])
);
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay13_col0 (
.clk_in(dqs_int_delay_in13),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[13])
);
// Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
dqs_delay dqs_delay13_col1 (
.clk_in(dqs_int_delay_in13),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col1[13])
);
// FIFO Write enable signal generation
fifo_0_wr_en fifo_00_wr_en_inst (
.clk (dqs0_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.dout (fifo_00_wr_en)
);
fifo_1_wr_en fifo_01_wr_en_inst (
.clk (dqs0_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_01_wr_en)
);
fifo_0_wr_en fifo_10_wr_en_inst (
.clk (dqs1_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.dout (fifo_10_wr_en)
);
fifo_1_wr_en fifo_11_wr_en_inst (
.clk (dqs1_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_11_wr_en)
);
fifo_0_wr_en fifo_20_wr_en_inst (
.clk (dqs2_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.dout (fifo_20_wr_en)
);
fifo_1_wr_en fifo_21_wr_en_inst (
.clk (dqs2_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_21_wr_en)
);
fifo_0_wr_en fifo_30_wr_en_inst (
.clk (dqs3_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.dout (fifo_30_wr_en)
);
fifo_1_wr_en fifo_31_wr_en_inst (
.clk (dqs3_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_31_wr_en)
);
fifo_0_wr_en fifo_40_wr_en_inst (
.clk (dqs4_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.dout (fifo_40_wr_en)
);
fifo_1_wr_en fifo_41_wr_en_inst (
.clk (dqs4_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_41_wr_en)
);
fifo_0_wr_en fifo_50_wr_en_inst (
.clk (dqs5_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.dout (fifo_50_wr_en)
);
fifo_1_wr_en fifo_51_wr_en_inst (
.clk (dqs5_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_51_wr_en)
);
fifo_0_wr_en fifo_60_wr_en_inst (
.clk (dqs6_delayed_col1_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.dout (fifo_60_wr_en)
);
fifo_1_wr_en fifo_61_wr_en_inst (
.clk (dqs6_delayed_col0),
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -