📄 data_read_56bit.v
字号:
.A3(fifo_90_wr_addr[3]),
.D(ddr_dq_in[37]),
.DPRA0(fifo_90_rd_addr[0]),
.DPRA1(fifo_90_rd_addr[1]),
.DPRA2(fifo_90_rd_addr[2]),
.DPRA3(fifo_90_rd_addr[3]),
.WCLK(dqs9_delayed_col1),
.WE(fifo_90_wr_en)
);
RAM16X1D fifo1_bit37
( .DPO(fifo_91_data_out[1]),
.SPO( ),
.A0(fifo_91_wr_addr[0]),
.A1(fifo_91_wr_addr[1]),
.A2(fifo_91_wr_addr[2]),
.A3(fifo_91_wr_addr[3]),
.D(ddr_dq_in[37]),
.DPRA0(fifo_91_rd_addr[0]),
.DPRA1(fifo_91_rd_addr[1]),
.DPRA2(fifo_91_rd_addr[2]),
.DPRA3(fifo_91_rd_addr[3]),
.WCLK(dqs9_delayed_col0_n),
.WE(fifo_91_wr_en)
);
RAM16X1D fifo0_bit38
( .DPO(fifo_90_data_out[2]),
.SPO( ),
.A0(fifo_90_wr_addr[0]),
.A1(fifo_90_wr_addr[1]),
.A2(fifo_90_wr_addr[2]),
.A3(fifo_90_wr_addr[3]),
.D(ddr_dq_in[38]),
.DPRA0(fifo_90_rd_addr[0]),
.DPRA1(fifo_90_rd_addr[1]),
.DPRA2(fifo_90_rd_addr[2]),
.DPRA3(fifo_90_rd_addr[3]),
.WCLK(dqs9_delayed_col1),
.WE(fifo_90_wr_en)
);
RAM16X1D fifo1_bit38
( .DPO(fifo_91_data_out[2]),
.SPO( ),
.A0(fifo_91_wr_addr[0]),
.A1(fifo_91_wr_addr[1]),
.A2(fifo_91_wr_addr[2]),
.A3(fifo_91_wr_addr[3]),
.D(ddr_dq_in[38]),
.DPRA0(fifo_91_rd_addr[0]),
.DPRA1(fifo_91_rd_addr[1]),
.DPRA2(fifo_91_rd_addr[2]),
.DPRA3(fifo_91_rd_addr[3]),
.WCLK(dqs9_delayed_col0_n),
.WE(fifo_91_wr_en)
);
RAM16X1D fifo0_bit39
( .DPO(fifo_90_data_out[3]),
.SPO( ),
.A0(fifo_90_wr_addr[0]),
.A1(fifo_90_wr_addr[1]),
.A2(fifo_90_wr_addr[2]),
.A3(fifo_90_wr_addr[3]),
.D(ddr_dq_in[39]),
.DPRA0(fifo_90_rd_addr[0]),
.DPRA1(fifo_90_rd_addr[1]),
.DPRA2(fifo_90_rd_addr[2]),
.DPRA3(fifo_90_rd_addr[3]),
.WCLK(dqs9_delayed_col1),
.WE(fifo_90_wr_en)
);
RAM16X1D fifo1_bit39
( .DPO(fifo_91_data_out[3]),
.SPO( ),
.A0(fifo_91_wr_addr[0]),
.A1(fifo_91_wr_addr[1]),
.A2(fifo_91_wr_addr[2]),
.A3(fifo_91_wr_addr[3]),
.D(ddr_dq_in[39]),
.DPRA0(fifo_91_rd_addr[0]),
.DPRA1(fifo_91_rd_addr[1]),
.DPRA2(fifo_91_rd_addr[2]),
.DPRA3(fifo_91_rd_addr[3]),
.WCLK(dqs9_delayed_col0_n),
.WE(fifo_91_wr_en)
);
// Nibble 10 Fifo instantiation
RAM16X1D fifo0_bit40
( .DPO (fifo_100_data_out[0]),
.SPO( ),
.A0(fifo_100_wr_addr[0]),
.A1 (fifo_100_wr_addr[1]),
.A2 (fifo_100_wr_addr[2]),
.A3 (fifo_100_wr_addr[3]),
.D (ddr_dq_in[40]),
.DPRA0(fifo_100_rd_addr[0]),
.DPRA1(fifo_100_rd_addr[1]),
.DPRA2(fifo_100_rd_addr[2]),
.DPRA3(fifo_100_rd_addr[3]),
.WCLK (dqs10_delayed_col1),
.WE (fifo_100_wr_en)
);
RAM16X1D fifo1_bit40
( .DPO (fifo_101_data_out[0]),
.SPO( ),
.A0 (fifo_101_wr_addr[0]),
.A1 (fifo_101_wr_addr[1]),
.A2 (fifo_101_wr_addr[2]),
.A3 (fifo_101_wr_addr[3]),
.D (ddr_dq_in[40]),
.DPRA0(fifo_101_rd_addr[0]),
.DPRA1(fifo_101_rd_addr[1]),
.DPRA2(fifo_101_rd_addr[2]),
.DPRA3(fifo_101_rd_addr[3]),
.WCLK (dqs10_delayed_col0_n),
.WE (fifo_101_wr_en)
);
RAM16X1D fifo0_bit41
( .DPO (fifo_100_data_out[1]),
.SPO( ),
.A0 (fifo_100_wr_addr[0]),
.A1 (fifo_100_wr_addr[1]),
.A2 (fifo_100_wr_addr[2]),
.A3 (fifo_100_wr_addr[3]),
.D (ddr_dq_in[41]),
.DPRA0(fifo_100_rd_addr[0]),
.DPRA1(fifo_100_rd_addr[1]),
.DPRA2(fifo_100_rd_addr[2]),
.DPRA3(fifo_100_rd_addr[3]),
.WCLK (dqs10_delayed_col1),
.WE (fifo_100_wr_en)
);
RAM16X1D fifo1_bit41
( .DPO (fifo_101_data_out[1]),
.SPO( ),
.A0 (fifo_101_wr_addr[0]),
.A1 (fifo_101_wr_addr[1]),
.A2 (fifo_101_wr_addr[2]),
.A3 (fifo_101_wr_addr[3]),
.D (ddr_dq_in[41]),
.DPRA0(fifo_101_rd_addr[0]),
.DPRA1(fifo_101_rd_addr[1]),
.DPRA2(fifo_101_rd_addr[2]),
.DPRA3(fifo_101_rd_addr[3]),
.WCLK (dqs10_delayed_col0_n),
.WE (fifo_101_wr_en)
);
RAM16X1D fifo0_bit42
( .DPO (fifo_100_data_out[2]),
.SPO( ),
.A0 (fifo_100_wr_addr[0]),
.A1 (fifo_100_wr_addr[1]),
.A2 (fifo_100_wr_addr[2]),
.A3 (fifo_100_wr_addr[3]),
.D (ddr_dq_in[42]),
.DPRA0(fifo_100_rd_addr[0]),
.DPRA1(fifo_100_rd_addr[1]),
.DPRA2(fifo_100_rd_addr[2]),
.DPRA3(fifo_100_rd_addr[3]),
.WCLK (dqs10_delayed_col1),
.WE (fifo_100_wr_en)
);
RAM16X1D fifo1_bit42
( .DPO (fifo_101_data_out[2]),
.SPO( ),
.A0 (fifo_101_wr_addr[0]),
.A1 (fifo_101_wr_addr[1]),
.A2 (fifo_101_wr_addr[2]),
.A3 (fifo_101_wr_addr[3]),
.D (ddr_dq_in[42]),
.DPRA0(fifo_101_rd_addr[0]),
.DPRA1(fifo_101_rd_addr[1]),
.DPRA2(fifo_101_rd_addr[2]),
.DPRA3(fifo_101_rd_addr[3]),
.WCLK (dqs10_delayed_col0_n),
.WE (fifo_101_wr_en)
);
RAM16X1D fifo0_bit43
( .DPO (fifo_100_data_out[3]),
.SPO( ),
.A0 (fifo_100_wr_addr[0]),
.A1 (fifo_100_wr_addr[1]),
.A2 (fifo_100_wr_addr[2]),
.A3 (fifo_100_wr_addr[3]),
.D (ddr_dq_in[43]),
.DPRA0(fifo_100_rd_addr[0]),
.DPRA1(fifo_100_rd_addr[1]),
.DPRA2(fifo_100_rd_addr[2]),
.DPRA3(fifo_100_rd_addr[3]),
.WCLK (dqs10_delayed_col1),
.WE (fifo_100_wr_en)
);
RAM16X1D fifo1_bit43
( .DPO (fifo_101_data_out[3]),
.SPO( ),
.A0 (fifo_101_wr_addr[0]),
.A1 (fifo_101_wr_addr[1]),
.A2 (fifo_101_wr_addr[2]),
.A3 (fifo_101_wr_addr[3]),
.D (ddr_dq_in[43]),
.DPRA0(fifo_101_rd_addr[0]),
.DPRA1(fifo_101_rd_addr[1]),
.DPRA2(fifo_101_rd_addr[2]),
.DPRA3(fifo_101_rd_addr[3]),
.WCLK (dqs10_delayed_col0_n),
.WE (fifo_101_wr_en)
);
// Nibble 11 Fifo instantiation
RAM16X1D fifo0_bit44
( .DPO (fifo_110_data_out[0]),
.SPO( ),
.A0 (fifo_110_wr_addr[0]),
.A1 (fifo_110_wr_addr[1]),
.A2 (fifo_110_wr_addr[2]),
.A3 (fifo_110_wr_addr[3]),
.D (ddr_dq_in[44]),
.DPRA0(fifo_110_rd_addr[0]),
.DPRA1(fifo_110_rd_addr[1]),
.DPRA2(fifo_110_rd_addr[2]),
.DPRA3(fifo_110_rd_addr[3]),
.WCLK (dqs11_delayed_col1),
.WE (fifo_110_wr_en)
);
RAM16X1D fifo1_bit44
( .DPO (fifo_111_data_out[0]),
.SPO( ),
.A0 (fifo_111_wr_addr[0]),
.A1 (fifo_111_wr_addr[1]),
.A2 (fifo_111_wr_addr[2]),
.A3 (fifo_111_wr_addr[3]),
.D (ddr_dq_in[44]),
.DPRA0(fifo_111_rd_addr[0]),
.DPRA1(fifo_111_rd_addr[1]),
.DPRA2(fifo_111_rd_addr[2]),
.DPRA3(fifo_111_rd_addr[3]),
.WCLK (dqs11_delayed_col0_n),
.WE (fifo_111_wr_en)
);
RAM16X1D fifo0_bit45
( .DPO (fifo_110_data_out[1]),
.SPO( ),
.A0 (fifo_110_wr_addr[0]),
.A1 (fifo_110_wr_addr[1]),
.A2 (fifo_110_wr_addr[2]),
.A3 (fifo_110_wr_addr[3]),
.D (ddr_dq_in[45]),
.DPRA0(fifo_110_rd_addr[0]),
.DPRA1(fifo_110_rd_addr[1]),
.DPRA2(fifo_110_rd_addr[2]),
.DPRA3(fifo_110_rd_addr[3]),
.WCLK (dqs11_delayed_col1),
.WE (fifo_110_wr_en)
);
RAM16X1D fifo1_bit45
( .DPO (fifo_111_data_out[1]),
.SPO( ),
.A0 (fifo_111_wr_addr[0]),
.A1 (fifo_111_wr_addr[1]),
.A2 (fifo_111_wr_addr[2]),
.A3 (fifo_111_wr_addr[3]),
.D (ddr_dq_in[45]),
.DPRA0(fifo_111_rd_addr[0]),
.DPRA1(fifo_111_rd_addr[1]),
.DPRA2(fifo_111_rd_addr[2]),
.DPRA3(fifo_111_rd_addr[3]),
.WCLK (dqs11_delayed_col0_n),
.WE (fifo_111_wr_en)
);
RAM16X1D fifo0_bit46
( .DPO (fifo_110_data_out[2]),
.SPO( ),
.A0 (fifo_110_wr_addr[0]),
.A1 (fifo_110_wr_addr[1]),
.A2 (fifo_110_wr_addr[2]),
.A3 (fifo_110_wr_addr[3]),
.D (ddr_dq_in[46]),
.DPRA0(fifo_110_rd_addr[0]),
.DPRA1(fifo_110_rd_addr[1]),
.DPRA2(fifo_110_rd_addr[2]),
.DPRA3(fifo_110_rd_addr[3]),
.WCLK (dqs11_delayed_col1),
.WE (fifo_110_wr_en)
);
RAM16X1D fifo1_bit46
( .DPO (fifo_111_data_out[2]),
.SPO( ),
.A0 (fifo_111_wr_addr[0]),
.A1 (fifo_111_wr_addr[1]),
.A2 (fifo_111_wr_addr[2]),
.A3 (fifo_111_wr_addr[3]),
.D (ddr_dq_in[46]),
.DPRA0(fifo_111_rd_addr[0]),
.DPRA1(fifo_111_rd_addr[1]),
.DPRA2(fifo_111_rd_addr[2]),
.DPRA3(fifo_111_rd_addr[3]),
.WCLK (dqs11_delayed_col0_n),
.WE (fifo_111_wr_en)
);
RAM16X1D fifo0_bit47
( .DPO (fifo_110_data_out[3]),
.SPO( ),
.A0 (fifo_110_wr_addr[0]),
.A1 (fifo_110_wr_addr[1]),
.A2 (fifo_110_wr_addr[2]),
.A3 (fifo_110_wr_addr[3]),
.D (ddr_dq_in[47]),
.DPRA0(fifo_110_rd_addr[0]),
.DPRA1(fifo_110_rd_addr[1]),
.DPRA2(fifo_110_rd_addr[2]),
.DPRA3(fifo_110_rd_addr[3]),
.WCLK (dqs11_delayed_col1),
.WE (fifo_110_wr_en)
);
RAM16X1D fifo1_bit47
( .DPO (fifo_111_data_out[3]),
.SPO( ),
.A0 (fifo_111_wr_addr[0]),
.A1 (fifo_111_wr_addr[1]),
.A2 (fifo_111_wr_addr[2]),
.A3 (fifo_111_wr_addr[3]),
.D (ddr_dq_in[47]),
.DPRA0(fifo_111_rd_addr[0]),
.DPRA1(fifo_111_rd_addr[1]),
.DPRA2(fifo_111_rd_addr[2]),
.DPRA3(fifo_111_rd_addr[3]),
.WCLK (dqs11_delayed_col0_n),
.WE (fifo_111_wr_en)
);
// Nibble 12 Fifo instantiation
RAM16X1D fifo0_bit48
( .DPO (fifo_120_data_out[0]),
.SPO( ),
.A0 (fifo_120_wr_addr[0]),
.A1 (fifo_120_wr_addr[1]),
.A2 (fifo_120_wr_addr[2]),
.A3 (fifo_120_wr_addr[3]),
.D (ddr_dq_in[48]),
.DPRA0(fifo_120_rd_addr[0]),
.DPRA1(fifo_120_rd_addr[1]),
.DPRA2(fifo_120_rd_addr[2]),
.DPRA3(fifo_120_rd_addr[3]),
.WCLK (dqs12_delayed_col1),
.WE (fifo_120_wr_en)
);
RAM16X1D fifo1_bit48
( .DPO (fifo_121_data_out[0]),
.SPO( ),
.A0 (fifo_121_wr_addr[0]),
.A1 (fifo_121_wr_addr[1]),
.A2 (fifo_121_wr_addr[2]),
.A3 (fifo_121_wr_addr[3]),
.D (ddr_dq_in[48]),
.DPRA0(fifo_121_rd_addr[0]),
.DPRA1(fifo_121_rd_addr[1]),
.DPRA2(fifo_121_rd_addr[2]),
.DPRA3(fifo_121_rd_addr[3]),
.WCLK⌨️ 快捷键说明
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