infrastructure_iobs_56bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

                          );

FDDRRSE DDRCLK5B_INST    ( .Q  (ddr1_clk5b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK6_INST    ( .Q  (ddr1_clk6_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK6B_INST    ( .Q  (ddr1_clk6b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK7_INST    ( .Q  (ddr1_clk7_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK7B_INST    ( .Q  (ddr1_clk7b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK8_INST    ( .Q  (ddr1_clk8_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK8B_INST    ( .Q  (ddr1_clk8b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
FDDRRSE DDRCLK9_INST    ( .Q  (ddr1_clk9_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK9B_INST    ( .Q  (ddr1_clk9b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );



FDDRRSE DDRCLK10_INST    ( .Q  (ddr1_clk10_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK10B_INST    ( .Q  (ddr1_clk10b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK11_INST    ( .Q  (ddr1_clk11_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK11B_INST    ( .Q  (ddr1_clk11b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK12_INST    ( .Q  (ddr1_clk12_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK12B_INST    ( .Q  (ddr1_clk12b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK13_INST    ( .Q  (ddr1_clk13_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK13B_INST    ( .Q  (ddr1_clk13b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

//---- ******************************************
//---- Ouput BUffers for ddr clk's and dimm clk's
//---- ******************************************


OBUF r1  ( .I(ddr1_clk0_q),  .O(ddr1_clk0));

OBUF r2  ( .I(ddr1_clk0b_q),  .O(ddr1_clk0b));

OBUF r3  ( .I(ddr1_clk1_q),  .O(ddr1_clk1));

OBUF r4  ( .I(ddr1_clk1b_q),  .O(ddr1_clk1b));

OBUF r5  ( .I(ddr1_clk2_q),  .O(ddr1_clk2));

OBUF r6  ( .I(ddr1_clk2b_q),  .O(ddr1_clk2b));

OBUF r7  ( .I(ddr1_clk3_q),  .O(ddr1_clk3));

OBUF r8  ( .I(ddr1_clk3b_q),  .O(ddr1_clk3b));

OBUF r9  ( .I(ddr1_clk4_q),  .O(ddr1_clk4));

OBUF r10  ( .I(ddr1_clk4b_q),  .O(ddr1_clk4b));

OBUF r17  ( .I(ddr1_clk5_q),  .O(ddr1_clk5));

OBUF r18  ( .I(ddr1_clk5b_q),  .O(ddr1_clk5b));

OBUF r19 ( .I(ddr1_clk6_q),  .O(ddr1_clk6));

OBUF r20  ( .I(ddr1_clk6b_q),  .O(ddr1_clk6b));

OBUF r21  ( .I(ddr1_clk7_q),  .O(ddr1_clk7));

OBUF r22  ( .I(ddr1_clk7b_q),  .O(ddr1_clk7b));

OBUF r23  ( .I(ddr1_clk8_q),  .O(ddr1_clk8));

OBUF r24  ( .I(ddr1_clk8b_q),  .O(ddr1_clk8b));

OBUF r25  ( .I(ddr1_clk9_q),  .O(ddr1_clk9));

OBUF r26  ( .I(ddr1_clk9b_q),  .O(ddr1_clk9b));

OBUF r27  ( .I(ddr1_clk10_q),  .O(ddr1_clk10));

OBUF r28  ( .I(ddr1_clk10b_q),  .O(ddr1_clk10b));

OBUF r29  ( .I(ddr1_clk11_q),  .O(ddr1_clk11));

OBUF r30  ( .I(ddr1_clk11b_q),  .O(ddr1_clk11b));

OBUF r31  ( .I(ddr1_clk12_q),  .O(ddr1_clk12));

OBUF r32  ( .I(ddr1_clk12b_q),  .O(ddr1_clk12b));

OBUF r33  ( .I(ddr1_clk13_q),  .O(ddr1_clk13));

OBUF r34  ( .I(ddr1_clk13b_q),  .O(ddr1_clk13b));


endmodule