📄 data_read_controller_56bit.v
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// FIFO WRITE POINTER DOUBLE DELAYED SIGNALS
always@(posedge clk90)
begin
if (reset90_r == 1'b1)
begin
fifo_00_wr_addr_2d <= 4'h0;
fifo_01_wr_addr_2d <= 4'h0;
end
else
begin
fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
end
end
// user data valid output signal from data path.
always@(posedge clk90)
begin
if (reset90_r ==1'b1)
u_data_val <= 1'b0;
else
u_data_val <= read_valid_data_0_1;
end
dqs_delay rst_dqs_div_delayed (
.clk_in (rst_dqs_div_in),
.sel_in (delay_sel),
.clk_out (rst_dqs_div)
);
//**********************************************************************************************************
// fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
//**********************************************************************************************************
rd_gray_cntr fifo_00_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_00_rd_addr)
);
rd_gray_cntr fifo_01_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_01_rd_addr)
);
rd_gray_cntr fifo_10_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_10_rd_addr)
);
rd_gray_cntr fifo_11_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_11_rd_addr)
);
rd_gray_cntr fifo_20_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_20_rd_addr)
);
rd_gray_cntr fifo_21_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_21_rd_addr)
);
rd_gray_cntr fifo_30_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_30_rd_addr)
);
rd_gray_cntr fifo_31_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_31_rd_addr)
);
rd_gray_cntr fifo_40_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_40_rd_addr)
);
rd_gray_cntr fifo_41_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_41_rd_addr)
);
rd_gray_cntr fifo_50_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_50_rd_addr)
);
rd_gray_cntr fifo_51_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_51_rd_addr)
);
rd_gray_cntr fifo_60_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_60_rd_addr)
);
rd_gray_cntr fifo_61_rd_addr_inst (
.clk (clk90),
.reset (reset90_r),
.cnt_en (read_valid_data_1_val),
.rgc_gcnt (fifo_61_rd_addr)
);
//**************************************************************************************************
// DQS Internal Delay Circuit implemented in LUTs
//**************************************************************************************************
// Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
dqs_delay dqs_delay0_col0 (
.clk_in(dqs_int_delay_in0),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[0])
);
dqs_delay dqs_delay1_col0 (
.clk_in(dqs_int_delay_in1),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[1])
);
dqs_delay dqs_delay2_col0 (
.clk_in(dqs_int_delay_in2),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[2])
);
dqs_delay dqs_delay3_col0 (
.clk_in(dqs_int_delay_in3),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[3])
);
dqs_delay dqs_delay4_col0 (
.clk_in(dqs_int_delay_in4),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[4])
);
dqs_delay dqs_delay5_col0 (
.clk_in(dqs_int_delay_in5),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[5])
);
dqs_delay dqs_delay6_col0 (
.clk_in(dqs_int_delay_in6),
.sel_in(delay_sel),
.clk_out(dqs_delayed_col0[6])
);
//*************************************************************************************
// FIFO Write enable signal generation
//*************************************************************************************
fifo_0_wr_en fifo_00_wr_en_inst (
.clk (dqs0_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.dout (fifo_00_wr_en)
);
fifo_1_wr_en fifo_01_wr_en_inst (
.clk (dqs0_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_0_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_01_wr_en)
);
fifo_0_wr_en fifo_10_wr_en_inst (
.clk (dqs1_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.dout (fifo_10_wr_en)
);
fifo_1_wr_en fifo_11_wr_en_inst (
.clk (dqs1_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_1_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_11_wr_en)
);
fifo_0_wr_en fifo_20_wr_en_inst (
.clk (dqs2_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.dout (fifo_20_wr_en)
);
fifo_1_wr_en fifo_21_wr_en_inst (
.clk (dqs2_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_2_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_21_wr_en)
);
fifo_0_wr_en fifo_30_wr_en_inst (
.clk (dqs3_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.dout (fifo_30_wr_en)
);
fifo_1_wr_en fifo_31_wr_en_inst (
.clk (dqs3_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_3_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_31_wr_en)
);
fifo_0_wr_en fifo_40_wr_en_inst (
.clk (dqs4_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.dout (fifo_40_wr_en)
);
fifo_1_wr_en fifo_41_wr_en_inst (
.clk (dqs4_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_4_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_41_wr_en)
);
fifo_0_wr_en fifo_50_wr_en_inst (
.clk (dqs5_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.dout (fifo_50_wr_en)
);
fifo_1_wr_en fifo_51_wr_en_inst (
.clk (dqs5_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_51_wr_en)
);
fifo_0_wr_en fifo_60_wr_en_inst (
.clk (dqs6_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.dout (fifo_60_wr_en)
);
fifo_1_wr_en fifo_61_wr_en_inst (
.clk (dqs6_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_61_wr_en)
);
//-------------------------------------------------------------------------------------------------
// write pointer gray counter instances
wr_gray_cntr fifo_00_wr_addr_inst (
.clk (dqs0_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_00_wr_en),
.wgc_gcnt (fifo_00_wr_addr)
);
wr_gray_cntr fifo_01_wr_addr_inst (
.clk (dqs0_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_01_wr_en),
.wgc_gcnt (fifo_01_wr_addr)
);
wr_gray_cntr fifo_10_wr_addr_inst (
.clk (dqs1_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_10_wr_en),
.wgc_gcnt (fifo_10_wr_addr)
);
wr_gray_cntr fifo_11_wr_addr_inst (
.clk (dqs1_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_11_wr_en),
.wgc_gcnt (fifo_11_wr_addr)
);
wr_gray_cntr fifo_20_wr_addr_inst (
.clk (dqs2_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_20_wr_en),
.wgc_gcnt (fifo_20_wr_addr)
);
wr_gray_cntr fifo_21_wr_addr_inst (
.clk (dqs2_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_21_wr_en),
.wgc_gcnt (fifo_21_wr_addr)
);
wr_gray_cntr fifo_30_wr_addr_inst (
.clk (dqs3_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_30_wr_en),
.wgc_gcnt (fifo_30_wr_addr)
);
wr_gray_cntr fifo_31_wr_addr_inst (
.clk (dqs3_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_31_wr_en),
.wgc_gcnt (fifo_31_wr_addr)
);
wr_gray_cntr fifo_40_wr_addr_inst (
.clk (dqs4_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_40_wr_en),
.wgc_gcnt (fifo_40_wr_addr)
);
wr_gray_cntr fifo_41_wr_addr_inst (
.clk (dqs4_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_41_wr_en),
.wgc_gcnt (fifo_41_wr_addr)
);
wr_gray_cntr fifo_50_wr_addr_inst (
.clk (dqs5_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_50_wr_en),
.wgc_gcnt (fifo_50_wr_addr)
);
wr_gray_cntr fifo_51_wr_addr_inst (
.clk (dqs5_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_51_wr_en),
.wgc_gcnt (fifo_51_wr_addr)
);
wr_gray_cntr fifo_60_wr_addr_inst (
.clk (dqs6_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_60_wr_en),
.wgc_gcnt (fifo_60_wr_addr)
);
wr_gray_cntr fifo_61_wr_addr_inst (
.clk (dqs6_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_61_wr_en),
.wgc_gcnt (fifo_61_wr_addr)
);
endmodule⌨️ 快捷键说明
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