📄 data_read_56bit.v
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.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit29
(.DPO(fifo_30_data_out[5]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col0),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit29
(.DPO(fifo_31_data_out[5]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit30
(.DPO(fifo_30_data_out[6]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col0),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit30
(.DPO(fifo_31_data_out[6]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit31
(.DPO(fifo_30_data_out[7]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col0),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit31
( .DPO(fifo_31_data_out[7]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
//- Byte4 instantiation
RAM16X1D fifo0_bit32
( .DPO(fifo_40_data_out[0]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[32]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit32
( .DPO(fifo_41_data_out[0]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[32]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit33
( .DPO(fifo_40_data_out[1]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[33]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit33
( .DPO(fifo_41_data_out[1]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[33]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit34
( .DPO(fifo_40_data_out[2]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[34]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit34
( .DPO(fifo_41_data_out[2]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[34]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit35
( .DPO(fifo_40_data_out[3]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[35]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit35
( .DPO(fifo_41_data_out[3]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[35]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit36
( .DPO(fifo_40_data_out[4]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[36]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit36
( .DPO(fifo_41_data_out[4]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[36]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit37
( .DPO(fifo_40_data_out[5]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[37]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit37
( .DPO(fifo_41_data_out[5]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[37]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit38
( .DPO(fifo_40_data_out[6]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[38]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit38
( .DPO(fifo_41_data_out[6]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[38]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit39
( .DPO(fifo_40_data_out[7]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[39]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit39
( .DPO(fifo_41_data_out[7]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[39]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
// Byte5 Fifo instantiation
RAM16X1D fifo0_bit40
( .DPO (fifo_50_data_out[0]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[40]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit40
( .DPO (fifo_51_data_out[0]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[40]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit41
( .DPO (fifo_50_data_out[1]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
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