data_write_56bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
//`include "parameters_56bit.v"
module    data_write_56bit   ( 

     user_input_data,    
	user_data_mask,
     clk90,              
     reset90_r,          
     reset270_r,         
     write_enable,       
     write_en_val,       
     write_data_falling, 
     write_data_rising,  
     data_mask_f,
     data_mask_r
     );


input     [111:0]user_input_data;
input     [13:0] user_data_mask;
input     clk90;              
input     reset90_r;          
input     reset270_r;         
input     write_enable;       
output    write_en_val;       
output    [55:0]write_data_falling; 
output    [55:0]write_data_rising;  
output    [6:0]data_mask_f;        
output    [6:0]data_mask_r;   

reg write_en_val;

reg write_en_P1;          
reg write_en_P2;          
reg write_en_P3;          
reg write_en_int;         
reg [111:0]write_data;    
reg [111:0]write_data1;   
reg [111:0]write_data2;   
reg [111:0]write_data3;   
reg [111:0]write_data4;   
reg [111:0]write_data5;   
reg [111:0]write_data6;   
reg [111:0]write_data_int;
reg [55:0]write_data270_1;
reg [55:0]write_data270_2;
reg [13:0] write_data_m;    
reg [13:0] write_data_m1;   
reg [13:0] write_data_m2;   
reg [13:0] write_data_m3;   
reg [13:0] write_data_m4;   
reg [13:0] write_data_m5;   
reg [13:0] write_data_m6;   
reg [13:0] write_data_mask;
reg [6:0] write_data_m270_1;
reg [6:0] write_data_m270_2;

  
  
  
//assign data_mask_f = 7'b0000000;
//assign data_mask_r = 7'b0000000;
     
// pipeline varables

always@(negedge clk90)
begin
// varable_in
end

assign write_data_rising  = write_data270_2;
assign write_data_falling = write_data[55:0];
assign data_mask_r = write_data_m270_2;
assign data_mask_f = write_data_mask[6:0];


////--------------------------------------------------------------------------------
// data path for write enable
always@(posedge clk90)
begin
        write_en_P1 <= write_enable;
        write_en_P2 <= write_en_P1;
        write_en_P3 <= write_en_P2;
end

always@(negedge clk90)
begin
     	write_en_int   <= write_en_P2;//P2
//     	write_en_val   <= write_en_int; //int;
//     	write_en_val   <= write_enable; //int;
     	write_en_val   <= write_en_P1; //int;

end

endmodule