data_read_controller_8bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

 `timescale 1ns/100ps
module data_read_controller_8bit(
     clk90,
     reset_r,
     reset90_r,
     rst_dqs_div_in,
     delay_sel,
     dqs_int_delay_in0,
     fifo0_rd_addr,
     fifo1_rd_addr,
     u_data_val,
     read_valid_data_1_val,
     fifo_00_wr_en_val,
     fifo_01_wr_en_val,
     fifo_00_wr_addr_val,
     fifo_01_wr_addr_val,
     dqs0_delayed_col1_val,
     dqs0_delayed_col0_val
      );

     input    clk90;
     input     reset_r;
     input     reset90_r;
     input     rst_dqs_div_in;
     input     [4:0] delay_sel;   
     input     dqs_int_delay_in0;
     input     [3:0] fifo0_rd_addr ;
     input     [3:0] fifo1_rd_addr ;
				
     output     u_data_val;
     output     read_valid_data_1_val;    
     output     fifo_00_wr_en_val;	
     output     fifo_01_wr_en_val;	
     output     [3:0] fifo_00_wr_addr_val;
     output     [3:0] fifo_01_wr_addr_val;
     output     dqs0_delayed_col1_val;
     output     dqs0_delayed_col0_val;
    


   wire [7:0] dqs_delayed_col0; 
   wire [7:0] dqs_delayed_col1; 

   wire fifo_00_empty;
   wire fifo_01_empty;

   wire [3:0] fifo_00_wr_addr;
   wire [3:0] fifo_01_wr_addr;
   

   wire read_valid_data_0_1;
   reg  read_valid_data_r; 
   reg  read_valid_data_r1; 
   wire dqs0_delayed_col0;
  
   wire dqs0_delayed_col1;
   
   wire fifo_00_wr_en;
  
   wire fifo_01_wr_en;
   
   reg [3:0] fifo_00_wr_addr_d;
   reg [3:0] fifo_00_wr_addr_2d;
   reg [3:0] fifo_00_wr_addr_3d;
   reg [3:0] fifo_01_wr_addr_d;
   reg [3:0] fifo_01_wr_addr_2d;
   reg [3:0] fifo_01_wr_addr_3d;
   wire [7:0] ddr_dq_in;
   wire [7:0] write_data270_1;
   wire [7:0] write_data270_2;
   wire rst_dqs_div;
   wire rst_dqs_div2;
   reg  rst_dqs_div2_r1;
   reg  rst_dqs_div2_r2;
   reg  rst_dqs_div2_r3;
   reg  rst_dqs_div2_r4;  
   
   wire rst_dqs_delay_0_n;
   
   wire rst_dqs_delay_0_n_1;
   
   wire dqs0_delayed_col0_n;
   
   wire dqs0_delayed_col1_n;
   
   wire rst;
   reg  u_data_val_r;

   
   assign dqs0_delayed_col0 = dqs_delayed_col0[0];
   assign dqs0_delayed_col1 = dqs_delayed_col1[0];
   assign fifo_00_wr_addr_val = fifo_00_wr_addr; 
   assign fifo_01_wr_addr_val = fifo_01_wr_addr; 
   assign fifo_00_wr_en_val   =	fifo_00_wr_en;
  
   assign fifo_01_wr_en_val   =	fifo_01_wr_en;
   

   assign dqs0_delayed_col1_val = dqs0_delayed_col1;
   

   assign dqs0_delayed_col0_val = dqs0_delayed_col0;
  

   assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;


   assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
  

   assign fifo_00_empty = (fifo0_rd_addr == fifo_00_wr_addr_3d) ? 1'b1 : 1'b0;
   assign fifo_01_empty = (fifo1_rd_addr == fifo_01_wr_addr_3d) ? 1'b1 : 1'b0;

   assign read_valid_data_0_1 = ((~fifo_00_empty) & (~fifo_01_empty));
   assign read_valid_data_1_val = (read_valid_data_0_1);
   assign u_data_val = u_data_val_r; 
   assign rst = reset_r | (rst_dqs_div2_r4 & (~rst_dqs_div2_r3));
   
   

   
   always@(posedge clk90)begin
      if(reset90_r)begin
         fifo_00_wr_addr_d <= 4'd0;
         fifo_01_wr_addr_d <= 4'd0;
         fifo_00_wr_addr_2d <= 4'd0;
         fifo_01_wr_addr_2d <= 4'd0;
         fifo_00_wr_addr_3d <= 4'd0;
         fifo_01_wr_addr_3d <= 4'd0;
      end
      else begin
         fifo_00_wr_addr_d <= fifo_00_wr_addr;
         fifo_01_wr_addr_d <= fifo_01_wr_addr;
         fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
         fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
         fifo_00_wr_addr_3d <= fifo_00_wr_addr_2d;
         fifo_01_wr_addr_3d <= fifo_01_wr_addr_2d;
      end
   end


   always@(posedge clk90)begin
      if(reset90_r)begin
         u_data_val_r <= 1'b0;
         read_valid_data_r <= 1'b0;
         read_valid_data_r1 <= 1'b0;
      end
      else begin
         read_valid_data_r <= read_valid_data_0_1;
         read_valid_data_r1 <= read_valid_data_r;
         u_data_val_r <= read_valid_data_r1;
      end
   end // always@ (posedge clk90)


     always@(posedge clk90)begin
      if(reset90_r)begin
	 rst_dqs_div2_r1 <= 1'b0;
         rst_dqs_div2_r2 <= 1'b0;
         rst_dqs_div2_r3 <= 1'b0;
         rst_dqs_div2_r4 <= 1'b0;   
      end
      else begin
         rst_dqs_div2_r1 <=rst_dqs_div2 ;
	 rst_dqs_div2_r2 <=rst_dqs_div2_r1 ;
	 rst_dqs_div2_r3 <=rst_dqs_div2_r2 ;
	 rst_dqs_div2_r4 <=rst_dqs_div2_r3 ;
      end
    end

   // rst_dqs_div instantation. 

   dqs_delay rst_dqs_div_delayed1 (.clk_in(rst_dqs_div_in), .sel_in(delay_sel), .clk_out(rst_dqs_div));
   dqs_delay rst_dqs_div_delayed2 (.clk_in(rst_dqs_div_in), .sel_in(delay_sel), .clk_out(rst_dqs_div2));


  //DQS Internal Delay Circuit implemented in LUTs

   dqs_delay dqs_delay0_col0(.clk_in(dqs_int_delay_in0), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[0]));
   dqs_delay dqs_delay0_col1(.clk_in(dqs_int_delay_in0), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[0]));
  

   // FIFO write enables
   
   fifo_0_wr_en fifo_00_wr_en_inst (.clk(dqs0_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
                                    .rst_dqs_delay_n(rst_dqs_delay_0_n), .dout(fifo_00_wr_en));
   fifo_1_wr_en fifo_01_wr_en_inst (.clk(dqs0_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_0_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_01_wr_en));
  



   //write pointer gray counter instances

   wr_gray_cntr fifo_00_wr_addr_inst (.clk(dqs0_delayed_col1), .reset(reset_r), .cnt_en(fifo_00_wr_en),
                                      .wgc_gcnt(fifo_00_wr_addr));
   wr_gray_cntr fifo_01_wr_addr_inst (.clk(dqs0_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_01_wr_en),
                                      .wgc_gcnt(fifo_01_wr_addr));
  


endmodule