data_path_iobs_8bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
`include "parameters_8bit.v"
module    data_path_iobs_8bit   ( 

    clk,               
    clk90,
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,             
    reset90_r,         
    dqs_reset,         
    dqs_enable,        
    ddr_dqs,           
    ddr_dq,            
    write_data_falling,
    write_data_rising, 
    write_en_val,      
    data_mask_f,       
    data_mask_r,       
    dqs_int_delay_in0, 
    ddr_dq_val,         
    ddr_dm           
);

input    clk;             
input	 clk90;
//XST_REMOVECOMMENT input  clk180;
//XST_REMOVECOMMENT input  clk270;             
input    reset90_r;       
input	 dqs_reset;         
input    dqs_enable;        
inout    ddr_dqs;          
inout    [7:0]ddr_dq;          
input	 [7:0]write_data_falling;
input    [7:0]write_data_rising; 
input    write_en_val;      
input    data_mask_f;   
input    data_mask_r;   
output    dqs_int_delay_in0; 
output    [7:0]ddr_dq_val;
output   [0:0] ddr_dm;

//SYN_REMOVECOMMENT wire clk270 /* synthesis syn_keep =1 */;   
//SYN_REMOVECOMMENT wire clk180 /* synthesis syn_keep =1 */;   

wire [7:0]ddr_dq_in;




//SYN_REMOVECOMMENT assign clk270  =  ~ clk90;
//SYN_REMOVECOMMENT assign clk180  =  ~ clk;

assign ddr_dq_val = ddr_dq_in;

ddr1_dm_8bit	ddr1_dm0	( 
                             .ddr_dm(ddr_dm),
                             .mask_falling (data_mask_f),
                             .mask_rising  (data_mask_r),
                             .clk90        (clk90),
                             .clk270       (clk270)
                            );



//***********************************************************************
//    Read Data Capture Module Instantiations
//***********************************************************************
// DQS IOB instantiations
//***********************************************************************

 ddr_dqs_iob  ddr_dqs_iob0 (
                              .clk            (clk),
                              .clk180         (clk180),
                              .ddr_dqs_reset  (dqs_reset),
                              .ddr_dqs_enable (dqs_enable),
                              .ddr_dqs        (ddr_dqs),
                              .dqs            (dqs_int_delay_in0)
			    );

//******************************************************************************************************************************
// DDR Data bit instantiations (72-bits)
//******************************************************************************************************************************            
 
 ddr_dq_iob  ddr_dq_iob0 
				(
      				.ddr_dq_inout       (ddr_dq[0]), 
      				.write_data_falling (write_data_falling[0]), 
      				.write_data_rising  (write_data_rising[0]),
      				.read_data_in       (ddr_dq_in[0]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob1 
				(
      				.ddr_dq_inout       (ddr_dq[1]), 
      				.write_data_falling (write_data_falling[1]), 
      				.write_data_rising  (write_data_rising[1]),
      				.read_data_in       (ddr_dq_in[1]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob2 
				(
      				.ddr_dq_inout       (ddr_dq[2]), 
      				.write_data_falling (write_data_falling[2]), 
      				.write_data_rising  (write_data_rising[2]),
      				.read_data_in       (ddr_dq_in[2]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob3 
				(
      				.ddr_dq_inout       (ddr_dq[3]), 
      				.write_data_falling (write_data_falling[3]), 
      				.write_data_rising  (write_data_rising[3]),
      				.read_data_in       (ddr_dq_in[3]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob4 
				(
      				.ddr_dq_inout       (ddr_dq[4]), 
      				.write_data_falling (write_data_falling[4]), 
      				.write_data_rising  (write_data_rising[4]),
      				.read_data_in       (ddr_dq_in[4]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
  
 ddr_dq_iob  ddr_dq_iob5 
				(
      				.ddr_dq_inout       (ddr_dq[5]), 
      				.write_data_falling (write_data_falling[5]), 
      				.write_data_rising  (write_data_rising[5]),
      				.read_data_in       (ddr_dq_in[5]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
 ddr_dq_iob  ddr_dq_iob6 
				(
      				.ddr_dq_inout       (ddr_dq[6]), 
      				.write_data_falling (write_data_falling[6]), 
      				.write_data_rising  (write_data_rising[6]),
      				.read_data_in       (ddr_dq_in[6]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
 ddr_dq_iob  ddr_dq_iob7 
				(
      				.ddr_dq_inout       (ddr_dq[7]), 
      				.write_data_falling (write_data_falling[7]), 
      				.write_data_rising  (write_data_rising[7]),
      				.read_data_in       (ddr_dq_in[7]),
      				.clk90              (clk90),
      				.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                        		     );
                        		     
                        		     
endmodule