data_read_controller_64bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

   assign dqs2_delayed_col0 = dqs_delayed_col0[2];
   assign dqs3_delayed_col0 = dqs_delayed_col0[3];
   assign dqs4_delayed_col0 = dqs_delayed_col0[4];
   assign dqs5_delayed_col0 = dqs_delayed_col0[5];
   assign dqs6_delayed_col0 = dqs_delayed_col0[6];
   assign dqs7_delayed_col0 = dqs_delayed_col0[7];

   assign dqs0_delayed_col1 = dqs_delayed_col1[0];
   assign dqs1_delayed_col1 = dqs_delayed_col1[1];
   assign dqs2_delayed_col1 = dqs_delayed_col1[2];
   assign dqs3_delayed_col1 = dqs_delayed_col1[3];
   assign dqs4_delayed_col1 = dqs_delayed_col1[4];
   assign dqs5_delayed_col1 = dqs_delayed_col1[5];
   assign dqs6_delayed_col1 = dqs_delayed_col1[6];
   assign dqs7_delayed_col1 = dqs_delayed_col1[7];


   assign fifo_00_wr_addr_val = fifo_00_wr_addr; 
   assign fifo_01_wr_addr_val = fifo_01_wr_addr; 
   assign fifo_10_wr_addr_val = fifo_10_wr_addr; 
   assign fifo_11_wr_addr_val = fifo_11_wr_addr; 
   assign fifo_20_wr_addr_val = fifo_20_wr_addr; 
   assign fifo_21_wr_addr_val = fifo_21_wr_addr; 
   assign fifo_30_wr_addr_val = fifo_30_wr_addr; 
   assign fifo_31_wr_addr_val = fifo_31_wr_addr; 
   assign fifo_40_wr_addr_val = fifo_40_wr_addr; 
   assign fifo_41_wr_addr_val = fifo_41_wr_addr; 
   assign fifo_50_wr_addr_val = fifo_50_wr_addr; 
   assign fifo_51_wr_addr_val = fifo_51_wr_addr; 
   assign fifo_60_wr_addr_val = fifo_60_wr_addr; 
   assign fifo_61_wr_addr_val = fifo_61_wr_addr; 
   assign fifo_70_wr_addr_val = fifo_70_wr_addr; 
   assign fifo_71_wr_addr_val = fifo_71_wr_addr; 




   assign fifo_00_wr_en_val   =	fifo_00_wr_en;
   assign fifo_10_wr_en_val   =	fifo_10_wr_en;
   assign fifo_20_wr_en_val   =	fifo_20_wr_en;
   assign fifo_30_wr_en_val   =	fifo_30_wr_en;
   assign fifo_40_wr_en_val   =	fifo_40_wr_en;
   assign fifo_50_wr_en_val   =	fifo_50_wr_en;
   assign fifo_60_wr_en_val   =	fifo_60_wr_en;
   assign fifo_70_wr_en_val   =	fifo_70_wr_en;
 
   assign fifo_01_wr_en_val   =	fifo_01_wr_en;
   assign fifo_11_wr_en_val   =	fifo_11_wr_en;
   assign fifo_21_wr_en_val   =	fifo_21_wr_en;
   assign fifo_31_wr_en_val   =	fifo_31_wr_en;
   assign fifo_41_wr_en_val   =	fifo_41_wr_en;
   assign fifo_51_wr_en_val   =	fifo_51_wr_en;
   assign fifo_61_wr_en_val   =	fifo_61_wr_en;
   assign fifo_71_wr_en_val   =	fifo_71_wr_en;


   assign dqs0_delayed_col1_val = dqs0_delayed_col1;
   assign dqs1_delayed_col1_val = dqs1_delayed_col1;
   assign dqs2_delayed_col1_val = dqs2_delayed_col1;
   assign dqs3_delayed_col1_val = dqs3_delayed_col1; 
   assign dqs4_delayed_col1_val = dqs4_delayed_col1;
   assign dqs5_delayed_col1_val = dqs5_delayed_col1;
   assign dqs6_delayed_col1_val = dqs6_delayed_col1;
   assign dqs7_delayed_col1_val = dqs7_delayed_col1;

   assign dqs0_delayed_col0_val = dqs0_delayed_col0;
   assign dqs1_delayed_col0_val = dqs1_delayed_col0;
   assign dqs2_delayed_col0_val = dqs2_delayed_col0;
   assign dqs3_delayed_col0_val = dqs3_delayed_col0; 
   assign dqs4_delayed_col0_val = dqs4_delayed_col0;
   assign dqs5_delayed_col0_val = dqs5_delayed_col0;
   assign dqs6_delayed_col0_val = dqs6_delayed_col0;
   assign dqs7_delayed_col0_val = dqs7_delayed_col0;

   assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
   assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
   assign dqs2_delayed_col0_n = ~ dqs2_delayed_col0;
   assign dqs3_delayed_col0_n = ~ dqs3_delayed_col0;
   assign dqs4_delayed_col0_n = ~ dqs4_delayed_col0;
   assign dqs5_delayed_col0_n = ~ dqs5_delayed_col0;
   assign dqs6_delayed_col0_n = ~ dqs6_delayed_col0;
   assign dqs7_delayed_col0_n = ~ dqs7_delayed_col0;

   assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
   assign dqs1_delayed_col1_n = ~ dqs1_delayed_col1;
   assign dqs2_delayed_col1_n = ~ dqs2_delayed_col1;
   assign dqs3_delayed_col1_n = ~ dqs3_delayed_col1;
   assign dqs4_delayed_col1_n = ~ dqs4_delayed_col1;
   assign dqs5_delayed_col1_n = ~ dqs5_delayed_col1;
   assign dqs6_delayed_col1_n = ~ dqs6_delayed_col1;
   assign dqs7_delayed_col1_n = ~ dqs7_delayed_col1;

   assign fifo_00_empty = (fifo0_rd_addr == fifo_00_wr_addr_3d) ? 1'b1 : 1'b0;
   assign fifo_01_empty = (fifo1_rd_addr == fifo_01_wr_addr_3d) ? 1'b1 : 1'b0;

   assign read_valid_data_0_1 = ((~fifo_00_empty) & (~fifo_01_empty));
   assign read_valid_data_1_val = (read_valid_data_0_1);
   assign u_data_val = u_data_val_r; 
   assign rst = reset_r | (rst_dqs_div2_r4 & (~rst_dqs_div2_r3));
   
   

   
   always@(posedge clk90)begin
      if(reset90_r)begin
         fifo_00_wr_addr_d <= 4'd0;
         fifo_01_wr_addr_d <= 4'd0;
         fifo_00_wr_addr_2d <= 4'd0;
         fifo_01_wr_addr_2d <= 4'd0;
         fifo_00_wr_addr_3d <= 4'd0;
         fifo_01_wr_addr_3d <= 4'd0;
      end
      else begin
         fifo_00_wr_addr_d <= fifo_00_wr_addr;
         fifo_01_wr_addr_d <= fifo_01_wr_addr;
         fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
         fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
         fifo_00_wr_addr_3d <= fifo_00_wr_addr_2d;
         fifo_01_wr_addr_3d <= fifo_01_wr_addr_2d;
      end
   end


   always@(posedge clk90)begin
      if(reset90_r)begin
         u_data_val_r <= 1'b0;
         read_valid_data_r <= 1'b0;
         read_valid_data_r1 <= 1'b0;
      end
      else begin
         read_valid_data_r <= read_valid_data_0_1;
         read_valid_data_r1 <= read_valid_data_r;
         u_data_val_r <= read_valid_data_r1;
      end
   end // always@ (posedge clk90)


     always@(posedge clk90)begin
      if(reset90_r)begin
	 rst_dqs_div2_r1 <= 1'b0;
         rst_dqs_div2_r2 <= 1'b0;
         rst_dqs_div2_r3 <= 1'b0;
         rst_dqs_div2_r4 <= 1'b0;   
      end
      else begin
         rst_dqs_div2_r1 <=rst_dqs_div2 ;
	 rst_dqs_div2_r2 <=rst_dqs_div2_r1 ;
	 rst_dqs_div2_r3 <=rst_dqs_div2_r2 ;
	 rst_dqs_div2_r4 <=rst_dqs_div2_r3 ;
      end
    end

   // rst_dqs_div instantation. 

   dqs_delay rst_dqs_div_delayed1 (.clk_in(rst_dqs_div_in), .sel_in(delay_sel), .clk_out(rst_dqs_div));
   dqs_delay rst_dqs_div_delayed2 (.clk_in(rst_dqs_div_in), .sel_in(delay_sel), .clk_out(rst_dqs_div2));


  //DQS Internal Delay Circuit implemented in LUTs

   dqs_delay dqs_delay0_col0(.clk_in(dqs_int_delay_in0), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[0]));
   dqs_delay dqs_delay0_col1(.clk_in(dqs_int_delay_in0), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[0]));
   dqs_delay dqs_delay1_col0(.clk_in(dqs_int_delay_in1), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[1]));
   dqs_delay dqs_delay1_col1(.clk_in(dqs_int_delay_in1), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[1]));
   dqs_delay dqs_delay2_col0(.clk_in(dqs_int_delay_in2), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[2]));
   dqs_delay dqs_delay2_col1(.clk_in(dqs_int_delay_in2), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[2]));
   dqs_delay dqs_delay3_col0(.clk_in(dqs_int_delay_in3), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[3]));
   dqs_delay dqs_delay3_col1(.clk_in(dqs_int_delay_in3), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[3]));
   dqs_delay dqs_delay4_col0(.clk_in(dqs_int_delay_in4), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[4]));
   dqs_delay dqs_delay4_col1(.clk_in(dqs_int_delay_in4), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[4]));
   dqs_delay dqs_delay5_col0(.clk_in(dqs_int_delay_in5), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[5]));
   dqs_delay dqs_delay5_col1(.clk_in(dqs_int_delay_in5), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[5]));
   dqs_delay dqs_delay6_col0(.clk_in(dqs_int_delay_in6), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[6]));
   dqs_delay dqs_delay6_col1(.clk_in(dqs_int_delay_in6), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[6]));
   dqs_delay dqs_delay7_col0(.clk_in(dqs_int_delay_in7), .sel_in(delay_sel), .clk_out(dqs_delayed_col0[7]));
   dqs_delay dqs_delay7_col1(.clk_in(dqs_int_delay_in7), .sel_in(delay_sel), .clk_out(dqs_delayed_col1[7]));


   // FIFO write enables
   
   fifo_0_wr_en fifo_00_wr_en_inst (.clk(dqs0_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
                                    .rst_dqs_delay_n(rst_dqs_delay_0_n), .dout(fifo_00_wr_en));
   fifo_1_wr_en fifo_01_wr_en_inst (.clk(dqs0_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_0_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_01_wr_en));
   fifo_0_wr_en fifo_10_wr_en_inst (.clk(dqs1_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
                                    .rst_dqs_delay_n(rst_dqs_delay_1_n), .dout(fifo_10_wr_en));
   fifo_1_wr_en fifo_11_wr_en_inst (.clk(dqs1_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_1_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_11_wr_en));
   fifo_0_wr_en fifo_20_wr_en_inst (.clk(dqs2_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
                                    .rst_dqs_delay_n(rst_dqs_delay_2_n), .dout(fifo_20_wr_en));
   fifo_1_wr_en fifo_21_wr_en_inst (.clk(dqs2_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_2_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_21_wr_en));
   fifo_0_wr_en fifo_30_wr_en_inst (.clk(dqs3_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div),
                                    .rst_dqs_delay_n(rst_dqs_delay_3_n), .dout(fifo_30_wr_en));
   fifo_1_wr_en fifo_31_wr_en_inst (.clk(dqs3_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_3_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_31_wr_en));
   fifo_0_wr_en fifo_40_wr_en_inst (.clk(dqs4_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div2),
                                    .rst_dqs_delay_n(rst_dqs_delay_4_n), .dout(fifo_40_wr_en));
   fifo_1_wr_en fifo_41_wr_en_inst (.clk(dqs4_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_4_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_41_wr_en));  
   fifo_0_wr_en fifo_50_wr_en_inst (.clk(dqs5_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div2),
                                    .rst_dqs_delay_n(rst_dqs_delay_5_n), .dout(fifo_50_wr_en));
   fifo_1_wr_en fifo_51_wr_en_inst (.clk(dqs5_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_5_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_51_wr_en));
   fifo_0_wr_en fifo_60_wr_en_inst (.clk(dqs6_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div2),
                                    .rst_dqs_delay_n(rst_dqs_delay_6_n), .dout(fifo_60_wr_en));
   fifo_1_wr_en fifo_61_wr_en_inst (.clk(dqs6_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_6_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_61_wr_en));
   fifo_0_wr_en fifo_70_wr_en_inst (.clk(dqs7_delayed_col1_n), .reset(reset_r), .din(rst_dqs_div2),
                                    .rst_dqs_delay_n(rst_dqs_delay_7_n), .dout(fifo_70_wr_en));
   fifo_1_wr_en fifo_71_wr_en_inst (.clk(dqs7_delayed_col0), .rst_dqs_delay_n(rst_dqs_delay_7_n),
                                    .reset(reset_r), .din(rst_dqs_div), .dout(fifo_71_wr_en));



   //write pointer gray counter instances

   wr_gray_cntr fifo_00_wr_addr_inst (.clk(dqs0_delayed_col1), .reset(reset_r), .cnt_en(fifo_00_wr_en),
                                      .wgc_gcnt(fifo_00_wr_addr));
   wr_gray_cntr fifo_01_wr_addr_inst (.clk(dqs0_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_01_wr_en),
                                      .wgc_gcnt(fifo_01_wr_addr));
   wr_gray_cntr fifo_10_wr_addr_inst (.clk(dqs1_delayed_col1), .reset(reset_r), .cnt_en(fifo_10_wr_en),
                                      .wgc_gcnt(fifo_10_wr_addr));
   wr_gray_cntr fifo_11_wr_addr_inst (.clk(dqs1_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_11_wr_en),
                                      .wgc_gcnt(fifo_11_wr_addr));
   wr_gray_cntr fifo_20_wr_addr_inst (.clk(dqs2_delayed_col1), .reset(reset_r), .cnt_en(fifo_20_wr_en),
                                      .wgc_gcnt(fifo_20_wr_addr));
   wr_gray_cntr fifo_21_wr_addr_inst (.clk(dqs2_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_21_wr_en),
                                      .wgc_gcnt(fifo_21_wr_addr));
   wr_gray_cntr fifo_30_wr_addr_inst (.clk(dqs3_delayed_col1), .reset(reset_r), .cnt_en(fifo_30_wr_en),
                                      .wgc_gcnt(fifo_30_wr_addr));
   wr_gray_cntr fifo_31_wr_addr_inst (.clk(dqs3_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_31_wr_en),
                                      .wgc_gcnt(fifo_31_wr_addr));
   wr_gray_cntr fifo_40_wr_addr_inst (.clk(dqs4_delayed_col1), .reset(reset_r), .cnt_en(fifo_40_wr_en),
                                      .wgc_gcnt(fifo_40_wr_addr));
   wr_gray_cntr fifo_41_wr_addr_inst (.clk(dqs4_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_41_wr_en),
                                      .wgc_gcnt(fifo_41_wr_addr));
   wr_gray_cntr fifo_50_wr_addr_inst (.clk(dqs5_delayed_col1), .reset(reset_r), .cnt_en(fifo_50_wr_en),
                                      .wgc_gcnt(fifo_50_wr_addr));
   wr_gray_cntr fifo_51_wr_addr_inst (.clk(dqs5_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_51_wr_en),
                                      .wgc_gcnt(fifo_51_wr_addr));
   wr_gray_cntr fifo_60_wr_addr_inst (.clk(dqs6_delayed_col1), .reset(reset_r), .cnt_en(fifo_60_wr_en),
                                      .wgc_gcnt(fifo_60_wr_addr));
   wr_gray_cntr fifo_61_wr_addr_inst (.clk(dqs6_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_61_wr_en),
                                      .wgc_gcnt(fifo_61_wr_addr));
   wr_gray_cntr fifo_70_wr_addr_inst (.clk(dqs7_delayed_col1), .reset(reset_r), .cnt_en(fifo_70_wr_en),
                                      .wgc_gcnt(fifo_70_wr_addr));
   wr_gray_cntr fifo_71_wr_addr_inst (.clk(dqs7_delayed_col0_n), .reset(reset_r), .cnt_en(fifo_71_wr_en),
                                      .wgc_gcnt(fifo_71_wr_addr));


endmodule