data_read_controller_64bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

 `timescale 1ns/100ps
module data_read_controller_64bit(
     clk90,
     reset_r,
     reset90_r,
     rst_dqs_div_in,
     delay_sel,
     dqs_int_delay_in0,
     dqs_int_delay_in1,
     dqs_int_delay_in2,
     dqs_int_delay_in3,
     dqs_int_delay_in4,
     dqs_int_delay_in5,
     dqs_int_delay_in6,
     dqs_int_delay_in7,
     fifo0_rd_addr,
     fifo1_rd_addr,
     u_data_val,
     read_valid_data_1_val,
     fifo_00_wr_en_val,
     fifo_10_wr_en_val,	
     fifo_20_wr_en_val,	
     fifo_30_wr_en_val,
     fifo_40_wr_en_val,	
     fifo_50_wr_en_val,	
     fifo_60_wr_en_val,	
     fifo_70_wr_en_val,
     fifo_01_wr_en_val,
     fifo_11_wr_en_val,	
     fifo_21_wr_en_val,	
     fifo_31_wr_en_val,
     fifo_41_wr_en_val,	
     fifo_51_wr_en_val,	
     fifo_61_wr_en_val,	
     fifo_71_wr_en_val,
     
     fifo_00_wr_addr_val,
     fifo_01_wr_addr_val,
     fifo_10_wr_addr_val,
     fifo_11_wr_addr_val,
     fifo_20_wr_addr_val,
     fifo_21_wr_addr_val,
     fifo_30_wr_addr_val,
     fifo_31_wr_addr_val,
     fifo_40_wr_addr_val,
     fifo_41_wr_addr_val,
     fifo_50_wr_addr_val,
     fifo_51_wr_addr_val,
     fifo_60_wr_addr_val,
     fifo_61_wr_addr_val,
     fifo_70_wr_addr_val,
     fifo_71_wr_addr_val,
     dqs0_delayed_col1_val,
     dqs1_delayed_col1_val,
     dqs2_delayed_col1_val,
     dqs3_delayed_col1_val,
     dqs4_delayed_col1_val,
     dqs5_delayed_col1_val,
     dqs6_delayed_col1_val,
     dqs7_delayed_col1_val,
     dqs0_delayed_col0_val,
     dqs1_delayed_col0_val,
     dqs2_delayed_col0_val,
     dqs3_delayed_col0_val,
     dqs4_delayed_col0_val,
     dqs5_delayed_col0_val,
     dqs6_delayed_col0_val,
     dqs7_delayed_col0_val);





     input    clk90;
     input     reset_r;
     input     reset90_r;
     input     rst_dqs_div_in;
     input     [4:0] delay_sel;   
     input     dqs_int_delay_in0;
     input     dqs_int_delay_in1;
     input     dqs_int_delay_in2;
     input     dqs_int_delay_in3 ;
     input     dqs_int_delay_in4 ;
     input     dqs_int_delay_in5 ;
     input     dqs_int_delay_in6 ;
     input     dqs_int_delay_in7 ;
     input     [3:0] fifo0_rd_addr ;
     input     [3:0] fifo1_rd_addr ;
					  
					  
     output     u_data_val;
     output     read_valid_data_1_val;    
     output     fifo_00_wr_en_val;	
     output     fifo_10_wr_en_val;	
     output     fifo_20_wr_en_val;	
     output     fifo_30_wr_en_val;
     output     fifo_40_wr_en_val;	
     output     fifo_50_wr_en_val;	
     output     fifo_60_wr_en_val;	
     output     fifo_70_wr_en_val;
     output     fifo_01_wr_en_val;	
     output     fifo_11_wr_en_val;	
     output     fifo_21_wr_en_val;	
     output     fifo_31_wr_en_val;
     output     fifo_41_wr_en_val;	
     output     fifo_51_wr_en_val;	
     output     fifo_61_wr_en_val;	
     output     fifo_71_wr_en_val;					  		  
     output     [3:0] fifo_00_wr_addr_val;
     output     [3:0] fifo_01_wr_addr_val;
     output     [3:0] fifo_10_wr_addr_val;
     output     [3:0] fifo_11_wr_addr_val;
     output     [3:0] fifo_20_wr_addr_val;
     output     [3:0] fifo_21_wr_addr_val;
     output     [3:0] fifo_30_wr_addr_val;
     output     [3:0] fifo_31_wr_addr_val;
     output     [3:0] fifo_40_wr_addr_val;
     output     [3:0] fifo_41_wr_addr_val;
     output     [3:0] fifo_50_wr_addr_val;
     output     [3:0] fifo_51_wr_addr_val;
     output     [3:0] fifo_60_wr_addr_val;
     output     [3:0] fifo_61_wr_addr_val;
     output     [3:0] fifo_70_wr_addr_val;
     output     [3:0] fifo_71_wr_addr_val;  
     output     dqs0_delayed_col1_val;
     output     dqs1_delayed_col1_val;
     output     dqs2_delayed_col1_val;
     output     dqs3_delayed_col1_val;
     output     dqs4_delayed_col1_val;
     output     dqs5_delayed_col1_val;
     output     dqs6_delayed_col1_val;
     output     dqs7_delayed_col1_val;		  
     output     dqs0_delayed_col0_val;
     output     dqs1_delayed_col0_val;
     output     dqs2_delayed_col0_val;
     output     dqs3_delayed_col0_val;
     output     dqs4_delayed_col0_val;
     output     dqs5_delayed_col0_val;
     output     dqs6_delayed_col0_val;
     output     dqs7_delayed_col0_val;


   wire [7:0] dqs_delayed_col0; 
   wire [7:0] dqs_delayed_col1; 

   wire fifo_00_empty;
   wire fifo_01_empty;

   wire [3:0] fifo_00_wr_addr;
   wire [3:0] fifo_01_wr_addr;
   wire [3:0] fifo_10_wr_addr;
   wire [3:0] fifo_11_wr_addr;
   wire [3:0] fifo_20_wr_addr;
   wire [3:0] fifo_21_wr_addr;
   wire [3:0] fifo_30_wr_addr;
   wire [3:0] fifo_31_wr_addr;
   wire [3:0] fifo_40_wr_addr;
   wire [3:0] fifo_41_wr_addr;
   wire [3:0] fifo_50_wr_addr;
   wire [3:0] fifo_51_wr_addr;
   wire [3:0] fifo_60_wr_addr;
   wire [3:0] fifo_61_wr_addr;
   wire [3:0] fifo_70_wr_addr;
   wire [3:0] fifo_71_wr_addr;

   wire read_valid_data_0_1;
   reg  read_valid_data_r; 
   reg  read_valid_data_r1; 
   wire dqs0_delayed_col0;
   wire dqs1_delayed_col0;
   wire dqs2_delayed_col0;
   wire dqs3_delayed_col0;
   wire dqs4_delayed_col0;
   wire dqs5_delayed_col0;
   wire dqs6_delayed_col0;
   wire dqs7_delayed_col0;
   wire dqs0_delayed_col1;
   wire dqs1_delayed_col1;
   wire dqs2_delayed_col1;
   wire dqs3_delayed_col1;
   wire dqs4_delayed_col1;
   wire dqs5_delayed_col1;
   wire dqs6_delayed_col1;
   wire dqs7_delayed_col1;
   wire fifo_00_wr_en;
   wire fifo_10_wr_en;
   wire fifo_20_wr_en;
   wire fifo_30_wr_en;
   wire fifo_40_wr_en;
   wire fifo_50_wr_en;
   wire fifo_60_wr_en;
   wire fifo_70_wr_en;
   wire fifo_01_wr_en;
   wire fifo_11_wr_en;
   wire fifo_21_wr_en;
   wire fifo_31_wr_en;
   wire fifo_41_wr_en;
   wire fifo_51_wr_en;
   wire fifo_61_wr_en;
   wire fifo_71_wr_en;
   reg [3:0] fifo_00_wr_addr_d;
   reg [3:0] fifo_00_wr_addr_2d;
   reg [3:0] fifo_00_wr_addr_3d;
   reg [3:0] fifo_01_wr_addr_d;
   reg [3:0] fifo_01_wr_addr_2d;
   reg [3:0] fifo_01_wr_addr_3d;
   wire [63:0] ddr_dq_in;
   wire [63:0] write_data270_1;
   wire [63:0] write_data270_2;
   wire rst_dqs_div;
   wire rst_dqs_div2;
   reg  rst_dqs_div2_r1;
   reg  rst_dqs_div2_r2;
   reg  rst_dqs_div2_r3;
   reg  rst_dqs_div2_r4;  
   
   wire rst_dqs_delay_0_n;
   wire rst_dqs_delay_1_n;
   wire rst_dqs_delay_2_n;
   wire rst_dqs_delay_3_n;
   wire rst_dqs_delay_4_n;
   wire rst_dqs_delay_5_n;
   wire rst_dqs_delay_6_n;
   wire rst_dqs_delay_7_n;
   wire rst_dqs_delay_0_n_1;
   wire rst_dqs_delay_1_n_1;
   wire rst_dqs_delay_2_n_1;
   wire rst_dqs_delay_3_n_1;
   wire rst_dqs_delay_4_n_1;
   wire rst_dqs_delay_5_n_1;
   wire rst_dqs_delay_6_n_1;
   wire rst_dqs_delay_7_n_1;
   wire dqs0_delayed_col0_n;
   wire dqs1_delayed_col0_n;
   wire dqs2_delayed_col0_n;
   wire dqs3_delayed_col0_n;
   wire dqs4_delayed_col0_n;
   wire dqs5_delayed_col0_n;
   wire dqs6_delayed_col0_n;
   wire dqs7_delayed_col0_n;
   wire dqs0_delayed_col1_n;
   wire dqs1_delayed_col1_n;
   wire dqs2_delayed_col1_n;
   wire dqs3_delayed_col1_n;
   wire dqs4_delayed_col1_n;
   wire dqs5_delayed_col1_n;
   wire dqs6_delayed_col1_n;
   wire dqs7_delayed_col1_n;
   wire rst;
   reg  u_data_val_r;

   
   assign dqs0_delayed_col0 = dqs_delayed_col0[0];
   assign dqs1_delayed_col0 = dqs_delayed_col0[1];