📄 data_read_64bit.v
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.DPRA2(fifo20_rd_addr_r[2]), .DPRA3(fifo20_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col1_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit23 (.DPO (fifo_20_data_out[7]), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(ddr_dq_in[23]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0), .WE(fifo_20_wr_en));
RAM16X1D fifo1_bit23 (.DPO (fifo_21_data_out[7]), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(ddr_dq_in[23]),
.DPRA0(fifo21_rd_addr_r[0]), .DPRA1(fifo21_rd_addr_r[1]),
.DPRA2(fifo21_rd_addr_r[2]), .DPRA3(fifo21_rd_addr_r[3]), .SPO(),
.WCLK(dqs2_delayed_col0_n), .WE(fifo_21_wr_en));
RAM16X1D fifo0_bit24 (.DPO (fifo_30_data_out[0]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[24]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit24 (.DPO (fifo_31_data_out[0]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[24]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit25 (.DPO (fifo_30_data_out[1]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[25]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit25 (.DPO (fifo_31_data_out[1]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[25]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit26 (.DPO (fifo_30_data_out[2]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[26]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit26 (.DPO (fifo_31_data_out[2]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[26]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit27 (.DPO (fifo_30_data_out[3]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[27]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit27 (.DPO (fifo_31_data_out[3]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[27]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit28 (.DPO (fifo_30_data_out[4]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[28]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit28 (.DPO (fifo_31_data_out[4]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[28]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit29 (.DPO (fifo_30_data_out[5]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[29]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit29 (.DPO (fifo_31_data_out[5]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[29]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit30 (.DPO (fifo_30_data_out[6]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[30]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit30 (.DPO (fifo_31_data_out[6]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[30]),
.DPRA0(fifo30_rd_addr_r[0]), .DPRA1(fifo30_rd_addr_r[1]),
.DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col1_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit31 (.DPO (fifo_30_data_out[7]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[31]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0), .WE(fifo_30_wr_en));
RAM16X1D fifo1_bit31 (.DPO (fifo_31_data_out[7]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[31]),
.DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]),
.DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
.WCLK(dqs3_delayed_col0_n), .WE(fifo_31_wr_en));
RAM16X1D fifo0_bit32 (.DPO (fifo_40_data_out[0]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[32]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit32 (.DPO (fifo_41_data_out[0]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[32]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));
RAM16X1D fifo0_bit33 (.DPO (fifo_40_data_out[1]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[33]),
.DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]),
.DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit33 (.DPO (fifo_41_data_out[1]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[33]),
.DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]),
.DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col0_n), .WE(fifo_41_wr_en));
RAM16X1D fifo0_bit34 (.DPO (fifo_40_data_out[2]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[34]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit34 (.DPO (fifo_41_data_out[2]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[34]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));
RAM16X1D fifo0_bit35 (.DPO (fifo_40_data_out[3]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[35]),
.DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]),
.DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit35 (.DPO (fifo_41_data_out[3]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[35]),
.DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]),
.DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col0_n), .WE(fifo_41_wr_en));
RAM16X1D fifo0_bit36 (.DPO (fifo_40_data_out[4]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[36]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit36 (.DPO (fifo_41_data_out[4]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[36]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));
RAM16X1D fifo0_bit37 (.DPO (fifo_40_data_out[5]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[37]),
.DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]),
.DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit37 (.DPO (fifo_41_data_out[5]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[37]),
.DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]),
.DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col0_n), .WE(fifo_41_wr_en));
RAM16X1D fifo0_bit38 (.DPO (fifo_40_data_out[6]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[38]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit38 (.DPO (fifo_41_data_out[6]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[38]),
.DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]),
.DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));
RAM16X1D fifo0_bit39 (.DPO (fifo_40_data_out[7]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[39]),
.DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]),
.DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
.WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en));
RAM16X1D fifo1_bit39 (.DPO (fifo_41_data_out[7]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[39]),
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