📄 data_read_controller_64bit.v
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.dout (fifo_50_wr_en)
);
fifo_1_wr_en fifo_51_wr_en_inst (
.clk (dqs5_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_5_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_51_wr_en)
);
fifo_0_wr_en fifo_60_wr_en_inst (
.clk (dqs6_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.dout (fifo_60_wr_en)
);
fifo_1_wr_en fifo_61_wr_en_inst (
.clk (dqs6_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_6_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_61_wr_en)
);
fifo_0_wr_en fifo_70_wr_en_inst (
.clk (dqs7_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_7_n),
.dout (fifo_70_wr_en)
);
fifo_1_wr_en fifo_71_wr_en_inst (
.clk (dqs7_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_7_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_71_wr_en)
);
fifo_0_wr_en fifo_80_wr_en_inst (
.clk (dqs8_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_8_n),
.dout (fifo_80_wr_en)
);
fifo_1_wr_en fifo_81_wr_en_inst (
.clk (dqs8_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_8_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_81_wr_en)
);
fifo_0_wr_en fifo_90_wr_en_inst (
.clk (dqs9_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_9_n),
.dout (fifo_90_wr_en)
);
fifo_1_wr_en fifo_91_wr_en_inst (
.clk (dqs9_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_9_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_91_wr_en)
);
fifo_0_wr_en fifo_100_wr_en_inst (
.clk (dqs10_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_10_n),
.dout (fifo_100_wr_en)
);
fifo_1_wr_en fifo_101_wr_en_inst (
.clk (dqs10_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_10_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_101_wr_en)
);
fifo_0_wr_en fifo_110_wr_en_inst (
.clk (dqs11_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_11_n),
.dout (fifo_110_wr_en)
);
fifo_1_wr_en fifo_111_wr_en_inst (
.clk (dqs11_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_11_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_111_wr_en)
);
fifo_0_wr_en fifo_120_wr_en_inst (
.clk (dqs12_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_12_n),
.dout (fifo_120_wr_en)
);
fifo_1_wr_en fifo_121_wr_en_inst (
.clk (dqs12_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_12_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_121_wr_en)
);
fifo_0_wr_en fifo_130_wr_en_inst (
.clk (dqs13_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_13_n),
.dout (fifo_130_wr_en)
);
fifo_1_wr_en fifo_131_wr_en_inst (
.clk (dqs13_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_13_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_131_wr_en)
);
fifo_0_wr_en fifo_140_wr_en_inst (
.clk (dqs14_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_14_n),
.dout (fifo_140_wr_en)
);
fifo_1_wr_en fifo_141_wr_en_inst (
.clk (dqs14_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_14_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_141_wr_en)
);
fifo_0_wr_en fifo_150_wr_en_inst (
.clk (dqs15_delayed_col0_n),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_15_n),
.dout (fifo_150_wr_en)
);
fifo_1_wr_en fifo_151_wr_en_inst (
.clk (dqs15_delayed_col0),
.rst_dqs_delay_n (rst_dqs_delay_15_n),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_151_wr_en)
);
//-------------------------------------------------------------------------------------------------
// write pointer gray counter instances
wr_gray_cntr fifo_00_wr_addr_inst (
.clk (dqs0_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_00_wr_en),
.wgc_gcnt (fifo_00_wr_addr)
);
wr_gray_cntr fifo_01_wr_addr_inst (
.clk (dqs0_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_01_wr_en),
.wgc_gcnt (fifo_01_wr_addr)
);
wr_gray_cntr fifo_10_wr_addr_inst (
.clk (dqs1_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_10_wr_en),
.wgc_gcnt (fifo_10_wr_addr)
);
wr_gray_cntr fifo_11_wr_addr_inst (
.clk (dqs1_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_11_wr_en),
.wgc_gcnt (fifo_11_wr_addr)
);
wr_gray_cntr fifo_20_wr_addr_inst (
.clk (dqs2_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_20_wr_en),
.wgc_gcnt (fifo_20_wr_addr)
);
wr_gray_cntr fifo_21_wr_addr_inst (
.clk (dqs2_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_21_wr_en),
.wgc_gcnt (fifo_21_wr_addr)
);
wr_gray_cntr fifo_30_wr_addr_inst (
.clk (dqs3_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_30_wr_en),
.wgc_gcnt (fifo_30_wr_addr)
);
wr_gray_cntr fifo_31_wr_addr_inst (
.clk (dqs3_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_31_wr_en),
.wgc_gcnt (fifo_31_wr_addr)
);
wr_gray_cntr fifo_40_wr_addr_inst (
.clk (dqs4_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_40_wr_en),
.wgc_gcnt (fifo_40_wr_addr)
);
wr_gray_cntr fifo_41_wr_addr_inst (
.clk (dqs4_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_41_wr_en),
.wgc_gcnt (fifo_41_wr_addr)
);
wr_gray_cntr fifo_50_wr_addr_inst (
.clk (dqs5_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_50_wr_en),
.wgc_gcnt (fifo_50_wr_addr)
);
wr_gray_cntr fifo_51_wr_addr_inst (
.clk (dqs5_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_51_wr_en),
.wgc_gcnt (fifo_51_wr_addr)
);
wr_gray_cntr fifo_60_wr_addr_inst (
.clk (dqs6_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_60_wr_en),
.wgc_gcnt (fifo_60_wr_addr)
);
wr_gray_cntr fifo_61_wr_addr_inst (
.clk (dqs6_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_61_wr_en),
.wgc_gcnt (fifo_61_wr_addr)
);
wr_gray_cntr fifo_70_wr_addr_inst (
.clk (dqs7_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_70_wr_en),
.wgc_gcnt (fifo_70_wr_addr)
);
wr_gray_cntr fifo_71_wr_addr_inst (
.clk (dqs7_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_71_wr_en),
.wgc_gcnt (fifo_71_wr_addr)
);
wr_gray_cntr fifo_80_wr_addr_inst (
.clk (dqs8_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_80_wr_en),
.wgc_gcnt (fifo_80_wr_addr)
);
wr_gray_cntr fifo_81_wr_addr_inst (
.clk (dqs8_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_81_wr_en),
.wgc_gcnt (fifo_81_wr_addr)
);
wr_gray_cntr fifo_90_wr_addr_inst (
.clk (dqs9_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_90_wr_en),
.wgc_gcnt (fifo_90_wr_addr)
);
wr_gray_cntr fifo_91_wr_addr_inst (
.clk (dqs9_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_91_wr_en),
.wgc_gcnt (fifo_91_wr_addr)
);
wr_gray_cntr fifo_100_wr_addr_inst (
.clk (dqs10_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_100_wr_en),
.wgc_gcnt (fifo_100_wr_addr)
);
wr_gray_cntr fifo_101_wr_addr_inst (
.clk (dqs10_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_101_wr_en),
.wgc_gcnt (fifo_101_wr_addr)
);
wr_gray_cntr fifo_110_wr_addr_inst (
.clk (dqs11_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_110_wr_en),
.wgc_gcnt (fifo_110_wr_addr)
);
wr_gray_cntr fifo_111_wr_addr_inst (
.clk (dqs11_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_111_wr_en),
.wgc_gcnt (fifo_111_wr_addr)
);
wr_gray_cntr fifo_120_wr_addr_inst (
.clk (dqs12_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_120_wr_en),
.wgc_gcnt (fifo_120_wr_addr)
);
wr_gray_cntr fifo_121_wr_addr_inst (
.clk (dqs12_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_121_wr_en),
.wgc_gcnt (fifo_121_wr_addr)
);
wr_gray_cntr fifo_130_wr_addr_inst (
.clk (dqs13_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_130_wr_en),
.wgc_gcnt (fifo_130_wr_addr)
);
wr_gray_cntr fifo_131_wr_addr_inst (
.clk (dqs13_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_131_wr_en),
.wgc_gcnt (fifo_131_wr_addr)
);
wr_gray_cntr fifo_140_wr_addr_inst (
.clk (dqs14_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_140_wr_en),
.wgc_gcnt (fifo_140_wr_addr)
);
wr_gray_cntr fifo_141_wr_addr_inst (
.clk (dqs14_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_141_wr_en),
.wgc_gcnt (fifo_141_wr_addr)
);
wr_gray_cntr fifo_150_wr_addr_inst (
.clk (dqs15_delayed_col0),
.reset (reset_r),
.cnt_en (fifo_150_wr_en),
.wgc_gcnt (fifo_150_wr_addr)
);
wr_gray_cntr fifo_151_wr_addr_inst (
.clk (dqs15_delayed_col0_n),
.reset (reset_r),
.cnt_en (fifo_151_wr_en),
.wgc_gcnt (fifo_151_wr_addr)
);
endmodule⌨️ 快捷键说明
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