📄 data_read_48bit.v
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.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
RAM16X1D fifo0_bit21
( .DPO(fifo_20_data_out[5]),
.SPO( ),
.A0(fifo_20_wr_addr[0]),
.A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]),
.A3(fifo_20_wr_addr[3]),
.D(ddr_dq_in[21]),
.DPRA0(fifo_20_rd_addr[0]),
.DPRA1(fifo_20_rd_addr[1]),
.DPRA2(fifo_20_rd_addr[2]),
.DPRA3(fifo_20_rd_addr[3]),
.WCLK(dqs2_delayed_col1),
.WE(fifo_20_wr_en)
);
RAM16X1D fifo1_bit21
( .DPO(fifo_21_data_out[5]),
.SPO( ),
.A0(fifo_21_wr_addr[0]),
.A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]),
.A3(fifo_21_wr_addr[3]),
.D(ddr_dq_in[21]),
.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
RAM16X1D fifo0_bit22
( .DPO(fifo_20_data_out[6]),
.SPO( ),
.A0(fifo_20_wr_addr[0]),
.A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]),
.A3(fifo_20_wr_addr[3]),
.D(ddr_dq_in[22]),
.DPRA0(fifo_20_rd_addr[0]),
.DPRA1(fifo_20_rd_addr[1]),
.DPRA2(fifo_20_rd_addr[2]),
.DPRA3(fifo_20_rd_addr[3]),
.WCLK(dqs2_delayed_col1),
.WE(fifo_20_wr_en)
);
RAM16X1D fifo1_bit22
( .DPO(fifo_21_data_out[6]),
.SPO( ),
.A0(fifo_21_wr_addr[0]),
.A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]),
.A3(fifo_21_wr_addr[3]),
.D(ddr_dq_in[22]),
.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
RAM16X1D fifo0_bit23
( .DPO(fifo_20_data_out[7]),
.SPO( ),
.A0(fifo_20_wr_addr[0]),
.A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]),
.A3(fifo_20_wr_addr[3]),
.D(ddr_dq_in[23]),
.DPRA0(fifo_20_rd_addr[0]),
.DPRA1(fifo_20_rd_addr[1]),
.DPRA2(fifo_20_rd_addr[2]),
.DPRA3(fifo_20_rd_addr[3]),
.WCLK(dqs2_delayed_col1),
.WE(fifo_20_wr_en)
);
RAM16X1D fifo1_bit23
( .DPO(fifo_21_data_out[7]),
.SPO( ),
.A0(fifo_21_wr_addr[0]),
.A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]),
.A3(fifo_21_wr_addr[3]),
.D(ddr_dq_in[23]),
.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
//Byte3 Fifo Instantiation
RAM16X1D fifo0_bit24
( .DPO(fifo_30_data_out[0]),
.SPO( ),
.A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[24]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit24
( .DPO(fifo_31_data_out[0]),
.SPO( ),
.A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[24]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit25
( .DPO(fifo_30_data_out[1]),
.SPO( ),
.A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[25]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit25
( .DPO(fifo_31_data_out[1]),
.SPO( ),
.A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[25]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit26
( .DPO(fifo_30_data_out[2]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[26]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit26
( .DPO(fifo_31_data_out[2]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[26]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit27
( .DPO(fifo_30_data_out[3]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[27]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit27
( .DPO(fifo_31_data_out[3]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[27]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit28
( .DPO(fifo_30_data_out[4]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[28]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit28
(.DPO(fifo_31_data_out[4]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[28]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit29
(.DPO(fifo_30_data_out[5]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit29
(.DPO(fifo_31_data_out[5]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit30
(.DPO(fifo_30_data_out[6]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit30
(.DPO(fifo_31_data_out[6]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit31
(.DPO(fifo_30_data_out[7]),
.SPO( ), .A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit31
( .DPO(fifo_31_data_out[7]),
.SPO( ), .A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
//- Byte4 instantiation
RAM16X1D fifo0_bit32
( .DPO(fifo_40_data_out[0]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[32]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col1),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit32
( .DPO(fifo_41_data_out[0]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[32]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit33
( .DPO(fifo_40_data_out[1]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[33]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col1),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit33
( .DPO(fifo_41_data_out[1]),
.SPO( ), .A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[33]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit34
( .DPO(fifo_40_data_out[2]),
.SPO( ), .A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
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