data_read_controller_48bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

wire dqs11_delayed_col0/* synthesis syn_keep=1 */;

wire dqs0_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs1_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs2_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs3_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs4_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs5_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs6_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs7_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs8_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs9_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs10_delayed_col1 /* synthesis syn_keep=1 */;	
wire dqs11_delayed_col1 /* synthesis syn_keep=1 */;	

wire dqs0_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs2_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs3_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs4_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs5_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs6_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs7_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs8_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs9_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs10_delayed_col0_n /* synthesis syn_keep=1 */;
wire dqs11_delayed_col0_n /* synthesis syn_keep=1 */;

wire dqs0_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs1_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs2_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs3_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs4_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs5_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs6_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs7_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs8_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs9_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs10_delayed_col1_n /* synthesis syn_keep=1 */;
wire dqs11_delayed_col1_n /* synthesis syn_keep=1 */;

wire 	   TIE_HIGH;


// FIFO WRITE ENABLE SIGNALS

wire 	fifo_00_wr_en;
wire 	fifo_01_wr_en;
wire 	fifo_10_wr_en;
wire 	fifo_11_wr_en;
wire 	fifo_20_wr_en;
wire 	fifo_21_wr_en;
wire 	fifo_30_wr_en;
wire 	fifo_31_wr_en;
wire 	fifo_40_wr_en;
wire 	fifo_41_wr_en;
wire 	fifo_50_wr_en;
wire 	fifo_51_wr_en;
wire 	fifo_60_wr_en;
wire 	fifo_61_wr_en;
wire 	fifo_70_wr_en;
wire 	fifo_71_wr_en;
wire 	fifo_80_wr_en;
wire 	fifo_81_wr_en;
wire 	fifo_90_wr_en;
wire 	fifo_91_wr_en;
wire 	fifo_100_wr_en;
wire 	fifo_101_wr_en;
wire 	fifo_110_wr_en;
wire 	fifo_111_wr_en;

wire rst_dqs_delay_0_n;
wire rst_dqs_delay_1_n;
wire rst_dqs_delay_2_n;
wire rst_dqs_delay_3_n;
wire rst_dqs_delay_4_n;
wire rst_dqs_delay_5_n;
wire rst_dqs_delay_6_n;
wire rst_dqs_delay_7_n;
wire rst_dqs_delay_8_n;
wire rst_dqs_delay_9_n;
wire rst_dqs_delay_10_n;
wire rst_dqs_delay_11_n;

// FIFO_WR_POINTER Delayed signals in clk90 domain

wire [3:0]fifo_00_rd_addr;
wire [3:0]fifo_01_rd_addr;
wire [3:0]fifo_10_rd_addr;
wire [3:0]fifo_11_rd_addr;
wire [3:0]fifo_20_rd_addr;
wire [3:0]fifo_21_rd_addr;
wire [3:0]fifo_30_rd_addr;
wire [3:0]fifo_31_rd_addr;
wire [3:0]fifo_40_rd_addr;
wire [3:0]fifo_41_rd_addr;
wire [3:0]fifo_50_rd_addr;
wire [3:0]fifo_51_rd_addr;
wire [3:0]fifo_60_rd_addr;
wire [3:0]fifo_61_rd_addr;
wire [3:0]fifo_70_rd_addr;
wire [3:0]fifo_71_rd_addr;
wire [3:0]fifo_80_rd_addr;
wire [3:0]fifo_81_rd_addr;
wire [3:0]fifo_90_rd_addr;
wire [3:0]fifo_91_rd_addr;
wire [3:0]fifo_100_rd_addr;
wire [3:0]fifo_101_rd_addr;
wire [3:0]fifo_110_rd_addr;
wire [3:0]fifo_111_rd_addr;

reg [3:0]fifo_00_wr_addr_d;
reg [3:0]fifo_00_wr_addr_2d;
reg [3:0]fifo_01_wr_addr_d;
reg [3:0]fifo_01_wr_addr_2d;


assign fifo_00_wr_addr_val = fifo_00_wr_addr; 
assign fifo_01_wr_addr_val = fifo_01_wr_addr; 
assign fifo_10_wr_addr_val = fifo_10_wr_addr; 
assign fifo_11_wr_addr_val = fifo_11_wr_addr; 
assign fifo_20_wr_addr_val = fifo_20_wr_addr; 
assign fifo_21_wr_addr_val = fifo_21_wr_addr; 
assign fifo_30_wr_addr_val = fifo_30_wr_addr; 
assign fifo_31_wr_addr_val = fifo_31_wr_addr; 
assign fifo_40_wr_addr_val = fifo_40_wr_addr; 
assign fifo_41_wr_addr_val = fifo_41_wr_addr; 
assign fifo_50_wr_addr_val = fifo_50_wr_addr; 
assign fifo_51_wr_addr_val = fifo_51_wr_addr; 
assign fifo_60_wr_addr_val = fifo_60_wr_addr; 
assign fifo_61_wr_addr_val = fifo_61_wr_addr; 
assign fifo_70_wr_addr_val = fifo_70_wr_addr; 
assign fifo_71_wr_addr_val = fifo_71_wr_addr; 
assign fifo_80_wr_addr_val = fifo_80_wr_addr; 
assign fifo_81_wr_addr_val = fifo_81_wr_addr;
assign fifo_90_wr_addr_val = fifo_90_wr_addr; 
assign fifo_91_wr_addr_val = fifo_91_wr_addr; 
assign fifo_100_wr_addr_val = fifo_100_wr_addr; 
assign fifo_101_wr_addr_val = fifo_101_wr_addr; 
assign fifo_110_wr_addr_val = fifo_110_wr_addr; 
assign fifo_111_wr_addr_val = fifo_111_wr_addr; 

assign fifo_00_wr_en_val		  =	fifo_00_wr_en;
assign fifo_10_wr_en_val		  =	fifo_10_wr_en;
assign fifo_20_wr_en_val		  =	fifo_20_wr_en;
assign fifo_30_wr_en_val		  =	fifo_30_wr_en;
assign fifo_40_wr_en_val		  =	fifo_40_wr_en;
assign fifo_50_wr_en_val		  =	fifo_50_wr_en;
assign fifo_60_wr_en_val		  =	fifo_60_wr_en;
assign fifo_70_wr_en_val		  =	fifo_70_wr_en;
assign fifo_80_wr_en_val		  =	fifo_80_wr_en;
assign fifo_90_wr_en_val		  =	fifo_90_wr_en;
assign fifo_100_wr_en_val		  =	fifo_100_wr_en;
assign fifo_110_wr_en_val		  =	fifo_110_wr_en;

assign fifo_01_wr_en_val		  =	fifo_01_wr_en;
assign fifo_11_wr_en_val		  =	fifo_11_wr_en;
assign fifo_21_wr_en_val		  =	fifo_21_wr_en;
assign fifo_31_wr_en_val		  =	fifo_31_wr_en;
assign fifo_41_wr_en_val		  =	fifo_41_wr_en;
assign fifo_51_wr_en_val		  =	fifo_51_wr_en;
assign fifo_61_wr_en_val		  =	fifo_61_wr_en;
assign fifo_71_wr_en_val		  =	fifo_71_wr_en;
assign fifo_81_wr_en_val		  =	fifo_81_wr_en;
assign fifo_91_wr_en_val		  =	fifo_91_wr_en;
assign fifo_101_wr_en_val		  =	fifo_101_wr_en;
assign fifo_111_wr_en_val		  =	fifo_111_wr_en;

assign dqs0_delayed_col1_val = dqs0_delayed_col1;
assign dqs1_delayed_col1_val = dqs1_delayed_col1;
assign dqs2_delayed_col1_val = dqs2_delayed_col1;
assign dqs3_delayed_col1_val = dqs3_delayed_col1; 
assign dqs4_delayed_col1_val = dqs4_delayed_col1;
assign dqs5_delayed_col1_val = dqs5_delayed_col1;
assign dqs6_delayed_col1_val = dqs6_delayed_col1;
assign dqs7_delayed_col1_val = dqs7_delayed_col1;
assign dqs8_delayed_col1_val = dqs8_delayed_col1;
assign dqs9_delayed_col1_val = dqs9_delayed_col1;
assign dqs10_delayed_col1_val = dqs10_delayed_col1;
assign dqs11_delayed_col1_val = dqs11_delayed_col1;

assign dqs0_delayed_col0_n_val =dqs0_delayed_col0_n;
assign dqs1_delayed_col0_n_val =dqs1_delayed_col0_n;
assign dqs2_delayed_col0_n_val =dqs2_delayed_col0_n;
assign dqs3_delayed_col0_n_val =dqs3_delayed_col0_n;
assign dqs4_delayed_col0_n_val =dqs4_delayed_col0_n;
assign dqs5_delayed_col0_n_val =dqs5_delayed_col0_n;
assign dqs6_delayed_col0_n_val =dqs6_delayed_col0_n;
assign dqs7_delayed_col0_n_val =dqs7_delayed_col0_n;
assign dqs8_delayed_col0_n_val =dqs8_delayed_col0_n;
assign dqs9_delayed_col0_n_val =dqs9_delayed_col0_n;
assign dqs10_delayed_col0_n_val =dqs10_delayed_col0_n;
assign dqs11_delayed_col0_n_val =dqs11_delayed_col0_n;

///////////////////////////////////////////////////////////////////////////

assign dqs0_delayed_col0 = dqs_delayed_col0[0];
assign dqs1_delayed_col0 = dqs_delayed_col0[1];
assign dqs2_delayed_col0 = dqs_delayed_col0[2];
assign dqs3_delayed_col0 = dqs_delayed_col0[3];
assign dqs4_delayed_col0 = dqs_delayed_col0[4];
assign dqs5_delayed_col0 = dqs_delayed_col0[5];
assign dqs6_delayed_col0 = dqs_delayed_col0[6];
assign dqs7_delayed_col0 = dqs_delayed_col0[7];
assign dqs8_delayed_col0 = dqs_delayed_col0[8];
assign dqs9_delayed_col0 = dqs_delayed_col0[9];
assign dqs10_delayed_col0 = dqs_delayed_col0[10];
assign dqs11_delayed_col0 = dqs_delayed_col0[11];

assign dqs0_delayed_col1 = dqs_delayed_col1[0];
assign dqs1_delayed_col1 = dqs_delayed_col1[1];
assign dqs2_delayed_col1 = dqs_delayed_col1[2];
assign dqs3_delayed_col1 = dqs_delayed_col1[3];
assign dqs4_delayed_col1 = dqs_delayed_col1[4];
assign dqs5_delayed_col1 = dqs_delayed_col1[5];
assign dqs6_delayed_col1 = dqs_delayed_col1[6];
assign dqs7_delayed_col1 = dqs_delayed_col1[7];
assign dqs8_delayed_col1 = dqs_delayed_col1[8];
assign dqs9_delayed_col1 = dqs_delayed_col1[9];
assign dqs10_delayed_col1 = dqs_delayed_col1[10];
assign dqs11_delayed_col1 = dqs_delayed_col1[11];

// dqsx_delayed_col0 negated signals

assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
assign dqs2_delayed_col0_n = ~ dqs2_delayed_col0;
assign dqs3_delayed_col0_n = ~ dqs3_delayed_col0;
assign dqs4_delayed_col0_n = ~ dqs4_delayed_col0;
assign dqs5_delayed_col0_n = ~ dqs5_delayed_col0;
assign dqs6_delayed_col0_n = ~ dqs6_delayed_col0;
assign dqs7_delayed_col0_n = ~ dqs7_delayed_col0;
assign dqs8_delayed_col0_n = ~ dqs8_delayed_col0;
assign dqs9_delayed_col0_n = ~ dqs8_delayed_col0;
assign dqs10_delayed_col0_n = ~ dqs10_delayed_col0;
assign dqs11_delayed_col0_n = ~ dqs11_delayed_col0;

// dqsx_delayed_col1 negated signals

assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
assign dqs1_delayed_col1_n = ~ dqs1_delayed_col1;
assign dqs2_delayed_col1_n = ~ dqs2_delayed_col1;
assign dqs3_delayed_col1_n = ~ dqs3_delayed_col1;
assign dqs4_delayed_col1_n = ~ dqs4_delayed_col1;
assign dqs5_delayed_col1_n = ~ dqs5_delayed_col1;
assign dqs6_delayed_col1_n = ~ dqs6_delayed_col1;
assign dqs7_delayed_col1_n = ~ dqs7_delayed_col1;
assign dqs8_delayed_col1_n = ~ dqs8_delayed_col1;
assign dqs9_delayed_col1_n = ~ dqs9_delayed_col1;
assign dqs10_delayed_col1_n = ~ dqs10_delayed_col1;
assign dqs11_delayed_col1_n = ~ dqs11_delayed_col1;

// TIE_HIGH assignment
assign TIE_HIGH = 1'b1;
assign  resetn  = ~ reset_r;
assign read_valid_data_0_1 = ( (~fifo_00_empty) && (~fifo_01_empty) );
assign read_valid_data_1_val   = read_valid_data_0_1;

assign fifo_00_empty  = (fifo_00_rd_addr[3:0] == fifo_00_wr_addr_2d[3:0] )? 1'b1 :1'b0;
assign fifo_01_empty   = (fifo_01_rd_addr[3:0] == fifo_01_wr_addr_2d[3:0] )? 1'b1 :1'b0;


assign fifo_00_rd_addr_val=fifo_00_rd_addr;
assign fifo_01_rd_addr_val=fifo_01_rd_addr;
assign fifo_10_rd_addr_val=fifo_10_rd_addr;
assign fifo_11_rd_addr_val=fifo_11_rd_addr;
assign fifo_20_rd_addr_val=fifo_20_rd_addr;
assign fifo_21_rd_addr_val=fifo_21_rd_addr;
assign fifo_30_rd_addr_val=fifo_30_rd_addr;
assign fifo_31_rd_addr_val=fifo_31_rd_addr;
assign fifo_40_rd_addr_val=fifo_40_rd_addr;
assign fifo_41_rd_addr_val=fifo_41_rd_addr;
assign fifo_50_rd_addr_val=fifo_50_rd_addr;
assign fifo_51_rd_addr_val=fifo_51_rd_addr;
assign fifo_60_rd_addr_val=fifo_60_rd_addr;
assign fifo_61_rd_addr_val=fifo_61_rd_addr;
assign fifo_70_rd_addr_val=fifo_70_rd_addr;
assign fifo_71_rd_addr_val=fifo_71_rd_addr;
assign fifo_80_rd_addr_val=fifo_80_rd_addr;
assign fifo_81_rd_addr_val=fifo_81_rd_addr;
assign fifo_90_rd_addr_val=fifo_90_rd_addr;
assign fifo_91_rd_addr_val=fifo_91_rd_addr;
assign fifo_100_rd_addr_val=fifo_100_rd_addr;
assign fifo_101_rd_addr_val=fifo_101_rd_addr;
assign fifo_110_rd_addr_val=fifo_110_rd_addr;
assign fifo_111_rd_addr_val=fifo_111_rd_addr;

// FIFO WRITE POINTER DELAYED SIGNALS
// To avoid meta-stability due to the domain crossing from ddr_dqs to clk90 

always@(posedge clk90)
begin
   if (reset90_r == 1'b1)
        begin
	fifo_00_wr_addr_d <= 4'h0;
	fifo_01_wr_addr_d <= 4'h0;
  	end
    else                                                   
    	begin
    	fifo_00_wr_addr_d <= fifo_00_wr_addr;
	fifo_01_wr_addr_d <= fifo_01_wr_addr;
	end
end

// FIFO WRITE POINTER DOUBLE DELAYED SIGNALS

always@(posedge clk90)
begin
   if (reset90_r == 1'b1) 
        begin
	fifo_00_wr_addr_2d <= 4'h0;
	fifo_01_wr_addr_2d <= 4'h0;
	end
    else                                                   
    	begin
    	fifo_00_wr_addr_2d <= fifo_00_wr_addr_d;
	fifo_01_wr_addr_2d <= fifo_01_wr_addr_d;
	end
 end
 
// user data valid output signal from data path.

always@(posedge clk90)
begin
   if (reset90_r ==1'b1)
   	u_data_val	<= 1'b0;
   else
        u_data_val  <= read_valid_data_0_1;
end	



dqs_delay rst_dqs_div_delayed   (                                                                          
	                              .clk_in   (rst_dqs_div_in),
	                              .sel_in   (delay_sel),                                
	                              .clk_out  (rst_dqs_div)                              
	                             );



// fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )  


rd_gray_cntr fifo_00_rd_addr_inst  (
				.clk      (clk90),
				.reset    (reset90_r),
				.cnt_en   (read_valid_data_1_val),
				.rgc_gcnt (fifo_00_rd_addr)
				  );