📄 data_read_48bit.v
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.SPO( ),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[2]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
RAM16X1D fifo0_bit3
( .DPO(fifo_00_data_out[3]),
.SPO( ),
.A0(fifo_00_wr_addr[0]),
.A1(fifo_00_wr_addr[1]),
.A2(fifo_00_wr_addr[2]),
.A3(fifo_00_wr_addr[3]),
.D(ddr_dq_in[3]),
.DPRA0(fifo_00_rd_addr[0]),
.DPRA1(fifo_00_rd_addr[1]),
.DPRA2(fifo_00_rd_addr[2]),
.DPRA3(fifo_00_rd_addr[3]),
.WCLK(dqs0_delayed_col1),
.WE(fifo_00_wr_en)
);
RAM16X1D fifo1_bit3
( .DPO(fifo_01_data_out[3]),
.SPO( ),
.A0(fifo_01_wr_addr[0]),
.A1(fifo_01_wr_addr[1]),
.A2(fifo_01_wr_addr[2]),
.A3(fifo_01_wr_addr[3]),
.D(ddr_dq_in[3]),
.DPRA0(fifo_01_rd_addr[0]),
.DPRA1(fifo_01_rd_addr[1]),
.DPRA2(fifo_01_rd_addr[2]),
.DPRA3(fifo_01_rd_addr[3]),
.WCLK(dqs0_delayed_col0_n),
.WE(fifo_01_wr_en)
);
// Nibble1 instantiation
RAM16X1D fifo0_bit4
( .DPO(fifo_10_data_out[0]),
.SPO( ),
.A0(fifo_10_wr_addr[0]),
.A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]),
.A3(fifo_10_wr_addr[3]),
.D(ddr_dq_in[4]),
.DPRA0(fifo_10_rd_addr[0]),
.DPRA1(fifo_10_rd_addr[1]),
.DPRA2(fifo_10_rd_addr[2]),
.DPRA3(fifo_10_rd_addr[3]),
.WCLK(dqs1_delayed_col1),
.WE(fifo_10_wr_en)
);
RAM16X1D fifo1_bit4
( .DPO(fifo_11_data_out[0]),
.SPO( ),
.A0(fifo_11_wr_addr[0]),
.A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]),
.A3(fifo_11_wr_addr[3]),
.D(ddr_dq_in[4]),
.DPRA0(fifo_11_rd_addr[0]),
.DPRA1(fifo_11_rd_addr[1]),
.DPRA2(fifo_11_rd_addr[2]),
.DPRA3(fifo_11_rd_addr[3]),
.WCLK(dqs1_delayed_col0_n),
.WE(fifo_11_wr_en)
);
RAM16X1D fifo0_bit5
( .DPO(fifo_10_data_out[1]),
.SPO( ),
.A0(fifo_10_wr_addr[0]),
.A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]),
.A3(fifo_10_wr_addr[3]),
.D(ddr_dq_in[5]),
.DPRA0(fifo_10_rd_addr[0]),
.DPRA1(fifo_10_rd_addr[1]),
.DPRA2(fifo_10_rd_addr[2]),
.DPRA3(fifo_10_rd_addr[3]),
.WCLK(dqs1_delayed_col1),
.WE(fifo_10_wr_en)
);
RAM16X1D fifo1_bit5
( .DPO(fifo_11_data_out[1]),
.SPO( ),
.A0(fifo_11_wr_addr[0]),
.A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]),
.A3(fifo_11_wr_addr[3]),
.D(ddr_dq_in[5]),
.DPRA0(fifo_11_rd_addr[0]),
.DPRA1(fifo_11_rd_addr[1]),
.DPRA2(fifo_11_rd_addr[2]),
.DPRA3(fifo_11_rd_addr[3]),
.WCLK(dqs1_delayed_col0_n),
.WE(fifo_11_wr_en)
);
RAM16X1D fifo0_bit6
( .DPO(fifo_10_data_out[2]),
.SPO( ),
.A0(fifo_10_wr_addr[0]),
.A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]),
.A3(fifo_10_wr_addr[3]),
.D(ddr_dq_in[6]),
.DPRA0(fifo_10_rd_addr[0]),
.DPRA1(fifo_10_rd_addr[1]),
.DPRA2(fifo_10_rd_addr[2]),
.DPRA3(fifo_10_rd_addr[3]),
.WCLK(dqs1_delayed_col1),
.WE(fifo_10_wr_en)
);
RAM16X1D fifo1_bit6
( .DPO(fifo_11_data_out[2]),
.SPO( ),
.A0(fifo_11_wr_addr[0]),
.A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]),
.A3(fifo_11_wr_addr[3]),
.D(ddr_dq_in[6]),
.DPRA0(fifo_11_rd_addr[0]),
.DPRA1(fifo_11_rd_addr[1]),
.DPRA2(fifo_11_rd_addr[2]),
.DPRA3(fifo_11_rd_addr[3]),
.WCLK(dqs1_delayed_col0_n),
.WE(fifo_11_wr_en)
);
RAM16X1D fifo0_bit7
( .DPO(fifo_10_data_out[3]),
.SPO( ),
.A0(fifo_10_wr_addr[0]),
.A1(fifo_10_wr_addr[1]),
.A2(fifo_10_wr_addr[2]),
.A3(fifo_10_wr_addr[3]),
.D(ddr_dq_in[7]),
.DPRA0(fifo_10_rd_addr[0]),
.DPRA1(fifo_10_rd_addr[1]),
.DPRA2(fifo_10_rd_addr[2]),
.DPRA3(fifo_10_rd_addr[3]),
.WCLK(dqs1_delayed_col1),
.WE(fifo_10_wr_en)
);
RAM16X1D fifo1_bit7
( .DPO(fifo_11_data_out[3]),
.SPO( ),
.A0(fifo_11_wr_addr[0]),
.A1(fifo_11_wr_addr[1]),
.A2(fifo_11_wr_addr[2]),
.A3(fifo_11_wr_addr[3]),
.D(ddr_dq_in[7]),
.DPRA0(fifo_11_rd_addr[0]),
.DPRA1(fifo_11_rd_addr[1]),
.DPRA2(fifo_11_rd_addr[2]),
.DPRA3(fifo_11_rd_addr[3]),
.WCLK(dqs1_delayed_col0_n),
.WE(fifo_11_wr_en)
);
// Nibble2 Fifo instantiation
RAM16X1D fifo0_bit8
( .DPO(fifo_20_data_out[0]),
.SPO( ),
.A0(fifo_20_wr_addr[0]),
.A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]),
.A3(fifo_20_wr_addr[3]),
.D(ddr_dq_in[8]),
.DPRA0(fifo_20_rd_addr[0]),
.DPRA1(fifo_20_rd_addr[1]),
.DPRA2(fifo_20_rd_addr[2]),
.DPRA3(fifo_20_rd_addr[3]),
.WCLK(dqs2_delayed_col1),
.WE(fifo_20_wr_en)
);
RAM16X1D fifo1_bit8
( .DPO(fifo_21_data_out[0]),
.SPO( ),
.A0(fifo_21_wr_addr[0]),
.A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]),
.A3(fifo_21_wr_addr[3]),
.D(ddr_dq_in[8]),
.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
RAM16X1D fifo0_bit9
( .DPO(fifo_20_data_out[1]),
.SPO( ),
.A0(fifo_20_wr_addr[0]),
.A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]),
.A3(fifo_20_wr_addr[3]),
.D(ddr_dq_in[9]),
.DPRA0(fifo_20_rd_addr[0]),
.DPRA1(fifo_20_rd_addr[1]),
.DPRA2(fifo_20_rd_addr[2]),
.DPRA3(fifo_20_rd_addr[3]),
.WCLK(dqs2_delayed_col1),
.WE(fifo_20_wr_en)
);
RAM16X1D fifo1_bit9
( .DPO(fifo_21_data_out[1]),
.SPO( ),
.A0(fifo_21_wr_addr[0]),
.A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]),
.A3(fifo_21_wr_addr[3]),
.D(ddr_dq_in[9]),
.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
RAM16X1D fifo0_bit10
( .DPO(fifo_20_data_out[2]),
.SPO( ),
.A0(fifo_20_wr_addr[0]),
.A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]),
.A3(fifo_20_wr_addr[3]),
.D(ddr_dq_in[10]),
.DPRA0(fifo_20_rd_addr[0]),
.DPRA1(fifo_20_rd_addr[1]),
.DPRA2(fifo_20_rd_addr[2]),
.DPRA3(fifo_20_rd_addr[3]),
.WCLK(dqs2_delayed_col1),
.WE(fifo_20_wr_en)
);
RAM16X1D fifo1_bit10
( .DPO(fifo_21_data_out[2]),
.SPO( ),
.A0(fifo_21_wr_addr[0]),
.A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]),
.A3(fifo_21_wr_addr[3]),
.D(ddr_dq_in[10]),
.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
RAM16X1D fifo0_bit11
( .DPO(fifo_20_data_out[3]),
.SPO( ),
.A0(fifo_20_wr_addr[0]),
.A1(fifo_20_wr_addr[1]),
.A2(fifo_20_wr_addr[2]),
.A3(fifo_20_wr_addr[3]),
.D(ddr_dq_in[11]),
.DPRA0(fifo_20_rd_addr[0]),
.DPRA1(fifo_20_rd_addr[1]),
.DPRA2(fifo_20_rd_addr[2]),
.DPRA3(fifo_20_rd_addr[3]),
.WCLK(dqs2_delayed_col1),
.WE(fifo_20_wr_en)
);
RAM16X1D fifo1_bit11
( .DPO(fifo_21_data_out[3]),
.SPO( ),
.A0(fifo_21_wr_addr[0]),
.A1(fifo_21_wr_addr[1]),
.A2(fifo_21_wr_addr[2]),
.A3(fifo_21_wr_addr[3]),
.D(ddr_dq_in[11]),
.DPRA0(fifo_21_rd_addr[0]),
.DPRA1(fifo_21_rd_addr[1]),
.DPRA2(fifo_21_rd_addr[2]),
.DPRA3(fifo_21_rd_addr[3]),
.WCLK(dqs2_delayed_col0_n),
.WE(fifo_21_wr_en)
);
// Nibble3 instantiation
RAM16X1D fifo0_bit12
( .DPO(fifo_30_data_out[0]),
.SPO( ),
.A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[12]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit12
( .DPO(fifo_31_data_out[0]),
.SPO( ),
.A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[12]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit13
( .DPO(fifo_30_data_out[1]),
.SPO( ),
.A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[13]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col1),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit13
( .DPO(fifo_31_data_out[1]),
.SPO( ),
.A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[13]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
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