cmp_data_48bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module    cmp_data_48bit(    
     clk,            
     data_valid,     
     lfsr_data,      
     read_data,      
     rst,            
     led_error_output, 
     data_valid_out 
     );

input  clk;
input  data_valid;
input  [95:0]lfsr_data/* synthesis syn_keep=1 */; 
input  [95:0]read_data;
input  rst;
output led_error_output;
output data_valid_out;


//attribute syn_keep : boolean;  -- Using Syn_Keep Derictive


reg  led_state;     
reg valid;
wire error;
   reg[5:0]      byte_err/* synthesis syn_preserve = 1 */;
   reg[5:0]      byte_err1/* synthesis syn_preserve = 1 */;
   reg           valid_1;
   reg           val_reg;
   reg[95:0]     read_data_reg;
      
   wire[15:0]    lfsr_0;
   wire[15:0]    lfsr_1;
   wire[15:0]    lfsr_2;
   wire[15:0]    lfsr_3;
   wire[15:0]    lfsr_4;
   wire[15:0]    lfsr_5;
 
   wire[15:0]    data_0;
   wire[15:0]    data_1;
   wire[15:0]    data_2;
   wire[15:0]    data_3;
   wire[15:0]    data_4;
   wire[15:0]    data_5;


//attribute syn_keep of lfsr_data : signal is true;


always @ (posedge clk)
begin
  if (rst == 1'b1)
    read_data_reg <= 112'd0;
  else
    read_data_reg <= read_data;
end

always @ (posedge clk)
begin
  if (rst == 1'b1)
    begin

      valid   <= 1'b0;
    end
  else
    begin

      valid   <= data_valid;
    end
end
assign data_valid_out = valid;


assign data_0         = read_data_reg[15:0];
assign data_1         = read_data_reg[31:16];
assign data_2         = read_data_reg[47:32];
assign data_3         = read_data_reg[63:48];
assign data_4        = read_data_reg[79:64];
assign data_5         = read_data_reg[95:80];
			
assign lfsr_0         = lfsr_data[15:0];
assign lfsr_1         = lfsr_data[31:16];
assign lfsr_2         = lfsr_data[47:32];
assign lfsr_3         = lfsr_data[63:48];
assign lfsr_4         = lfsr_data[79:64];
assign lfsr_5         = lfsr_data[95:80];

always @ (posedge clk)
begin
   if (rst == 1'b1)
     begin
        byte_err <= 6'b000000;
	byte_err1 <= 6'b000000;
	val_reg <= 1'b0;
     end
   else
     begin
	val_reg <= valid;
	byte_err[0] <= (data_0[7:0] != lfsr_0[7:0]);
	byte_err[1] <= (data_1[7:0] != lfsr_1[7:0]);
	byte_err[2] <= (data_2[7:0] != lfsr_2[7:0]);
	byte_err[3] <= (data_3[7:0] != lfsr_3[7:0]);
	byte_err[4] <= (data_4[7:0] != lfsr_4[7:0]);
	byte_err[5] <= (data_5[7:0] != lfsr_5[7:0]);
	byte_err1[0] <= (data_0[15:8] != lfsr_0[15:8]);
	byte_err1[1] <= (data_1[15:8] != lfsr_1[15:8]);
	byte_err1[2] <= (data_2[15:8] != lfsr_2[15:8]);
	byte_err1[3] <= (data_3[15:8] != lfsr_3[15:8]);
	byte_err1[4] <= (data_4[15:8] != lfsr_4[15:8]);
	byte_err1[5] <= (data_5[15:8] != lfsr_5[15:8]);
     end
end // always @ (posedge clk)
   
   assign error = ((|(byte_err[5:0])) || (|(byte_err1[5:0]))) && val_reg;


 // LED error output
always @ (posedge clk)
begin
      if (rst == 1'b1)
          led_state <= 1'b0;  // no error
      else
       begin
         case(led_state)
         1'b0 : begin
                if (error == 1'b1)
                  begin  
                      led_state <= 1'b1;  // Error
                      $display($time, " ### LED_ERROR : byte_err[0]= %b , byte_err[0]= %b ###",byte_err[0],byte_err[1]);
                      $finish;
                  end       
                else
                     led_state <= 1'b0;  // No Error
                end
          1'b1 : led_state <= 1'b1;
          default : led_state <= 1'b0;
         endcase
       end
end                   
assign led_error_output = (led_state == 1'b1) ? 1'b1 : 1'b0;
              


endmodule