data_read_48bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

                          .DPRA2(fifo30_rd_addr_r[2]), .DPRA3(fifo30_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs3_delayed_col1_n), .WE(fifo_31_wr_en));

   RAM16X1D fifo0_bit31  (.DPO (fifo_30_data_out[7]), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]),
                          .A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(ddr_dq_in[31]),
                          .DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]), 
                          .DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs3_delayed_col0), .WE(fifo_30_wr_en));

   RAM16X1D fifo1_bit31  (.DPO (fifo_31_data_out[7]), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]),
                          .A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(ddr_dq_in[31]),
                          .DPRA0(fifo31_rd_addr_r[0]), .DPRA1(fifo31_rd_addr_r[1]), 
                          .DPRA2(fifo31_rd_addr_r[2]), .DPRA3(fifo31_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs3_delayed_col0_n), .WE(fifo_31_wr_en));



   RAM16X1D fifo0_bit32  (.DPO (fifo_40_data_out[0]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[32]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));

   RAM16X1D fifo1_bit32  (.DPO (fifo_41_data_out[0]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[32]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));

   RAM16X1D fifo0_bit33  (.DPO (fifo_40_data_out[1]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[33]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en));

   RAM16X1D fifo1_bit33  (.DPO (fifo_41_data_out[1]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[33]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0_n), .WE(fifo_41_wr_en));

  RAM16X1D fifo0_bit34  (.DPO (fifo_40_data_out[2]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[34]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));

   RAM16X1D fifo1_bit34  (.DPO (fifo_41_data_out[2]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[34]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));

   RAM16X1D fifo0_bit35  (.DPO (fifo_40_data_out[3]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[35]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en)); 

   RAM16X1D fifo1_bit35  (.DPO (fifo_41_data_out[3]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[35]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0_n), .WE(fifo_41_wr_en));


   RAM16X1D fifo0_bit36  (.DPO (fifo_40_data_out[4]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[36]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));

   RAM16X1D fifo1_bit36  (.DPO (fifo_41_data_out[4]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[36]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));

   RAM16X1D fifo0_bit37  (.DPO (fifo_40_data_out[5]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[37]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en));

   RAM16X1D fifo1_bit37  (.DPO (fifo_41_data_out[5]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[37]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0_n), .WE(fifo_41_wr_en));

   RAM16X1D fifo0_bit38  (.DPO (fifo_40_data_out[6]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[38]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1), .WE(fifo_40_wr_en));

   RAM16X1D fifo1_bit38  (.DPO (fifo_41_data_out[6]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[38]),
                          .DPRA0(fifo40_rd_addr_r[0]), .DPRA1(fifo40_rd_addr_r[1]), 
                          .DPRA2(fifo40_rd_addr_r[2]), .DPRA3(fifo40_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col1_n), .WE(fifo_41_wr_en));

   RAM16X1D fifo0_bit39  (.DPO (fifo_40_data_out[7]), .A0(fifo_40_wr_addr[0]), .A1(fifo_40_wr_addr[1]),
                          .A2(fifo_40_wr_addr[2]), .A3(fifo_40_wr_addr[3]), .D(ddr_dq_in[39]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0), .WE(fifo_40_wr_en));

   RAM16X1D fifo1_bit39  (.DPO (fifo_41_data_out[7]), .A0(fifo_41_wr_addr[0]), .A1(fifo_41_wr_addr[1]),
                          .A2(fifo_41_wr_addr[2]), .A3(fifo_41_wr_addr[3]), .D(ddr_dq_in[39]),
                          .DPRA0(fifo41_rd_addr_r[0]), .DPRA1(fifo41_rd_addr_r[1]), 
                          .DPRA2(fifo41_rd_addr_r[2]), .DPRA3(fifo41_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs4_delayed_col0_n), .WE(fifo_41_wr_en));



   RAM16X1D fifo0_bit40  (.DPO (fifo_50_data_out[0]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[40]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit40  (.DPO (fifo_51_data_out[0]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[40]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1_n), .WE(fifo_51_wr_en));

   RAM16X1D fifo0_bit41  (.DPO (fifo_50_data_out[1]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[41]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit41  (.DPO (fifo_51_data_out[1]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[41]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0_n), .WE(fifo_51_wr_en));

  RAM16X1D fifo0_bit42  (.DPO (fifo_50_data_out[2]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[42]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit42  (.DPO (fifo_51_data_out[2]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[42]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1_n), .WE(fifo_51_wr_en));

   RAM16X1D fifo0_bit43  (.DPO (fifo_50_data_out[3]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[43]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit43  (.DPO (fifo_51_data_out[3]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[43]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0_n), .WE(fifo_51_wr_en));


   RAM16X1D fifo0_bit44  (.DPO (fifo_50_data_out[4]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[44]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit44  (.DPO (fifo_51_data_out[4]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[44]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1_n), .WE(fifo_51_wr_en));

   RAM16X1D fifo0_bit45  (.DPO (fifo_50_data_out[5]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[45]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit45  (.DPO (fifo_51_data_out[5]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[45]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0_n), .WE(fifo_51_wr_en));

   RAM16X1D fifo0_bit46  (.DPO (fifo_50_data_out[6]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[46]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit46  (.DPO (fifo_51_data_out[6]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[46]),
                          .DPRA0(fifo50_rd_addr_r[0]), .DPRA1(fifo50_rd_addr_r[1]), 
                          .DPRA2(fifo50_rd_addr_r[2]), .DPRA3(fifo50_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col1_n), .WE(fifo_51_wr_en));

   RAM16X1D fifo0_bit47  (.DPO (fifo_50_data_out[7]), .A0(fifo_50_wr_addr[0]), .A1(fifo_50_wr_addr[1]),
                          .A2(fifo_50_wr_addr[2]), .A3(fifo_50_wr_addr[3]), .D(ddr_dq_in[47]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0), .WE(fifo_50_wr_en));

   RAM16X1D fifo1_bit47  (.DPO (fifo_51_data_out[7]), .A0(fifo_51_wr_addr[0]), .A1(fifo_51_wr_addr[1]),
                          .A2(fifo_51_wr_addr[2]), .A3(fifo_51_wr_addr[3]), .D(ddr_dq_in[47]),
                          .DPRA0(fifo51_rd_addr_r[0]), .DPRA1(fifo51_rd_addr_r[1]), 
                          .DPRA2(fifo51_rd_addr_r[2]), .DPRA3(fifo51_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs5_delayed_col0_n), .WE(fifo_51_wr_en));



endmodule