📄 data_read_48bit.v
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.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit25
( .DPO(fifo_61_data_out[1]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[25]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
RAM16X1D fifo0_bit26
( .DPO(fifo_60_data_out[2]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[26]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit26
( .DPO(fifo_61_data_out[2]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[26]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
RAM16X1D fifo0_bit27
( .DPO(fifo_60_data_out[3]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[27]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit27
( .DPO(fifo_61_data_out[3]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[27]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
//- Nibble7 instantiation
RAM16X1D fifo0_bit28
( .DPO(fifo_70_data_out[0]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[28]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit28
(.DPO(fifo_71_data_out[0]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[28]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
RAM16X1D fifo0_bit29
(.DPO(fifo_70_data_out[1]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit29
(.DPO(fifo_71_data_out[1]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[29]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
RAM16X1D fifo0_bit30
(.DPO(fifo_70_data_out[2]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit30
(.DPO(fifo_71_data_out[2]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[30]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
RAM16X1D fifo0_bit31
(.DPO(fifo_70_data_out[3]),
.SPO( ),
.A0(fifo_70_wr_addr[0]),
.A1(fifo_70_wr_addr[1]),
.A2(fifo_70_wr_addr[2]),
.A3(fifo_70_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_70_rd_addr[0]),
.DPRA1(fifo_70_rd_addr[1]),
.DPRA2(fifo_70_rd_addr[2]),
.DPRA3(fifo_70_rd_addr[3]),
.WCLK(dqs7_delayed_col0),
.WE(fifo_70_wr_en)
);
RAM16X1D fifo1_bit31
( .DPO(fifo_71_data_out[3]),
.SPO( ),
.A0(fifo_71_wr_addr[0]),
.A1(fifo_71_wr_addr[1]),
.A2(fifo_71_wr_addr[2]),
.A3(fifo_71_wr_addr[3]),
.D(ddr_dq_in[31]),
.DPRA0(fifo_71_rd_addr[0]),
.DPRA1(fifo_71_rd_addr[1]),
.DPRA2(fifo_71_rd_addr[2]),
.DPRA3(fifo_71_rd_addr[3]),
.WCLK(dqs7_delayed_col0_n),
.WE(fifo_71_wr_en)
);
//- Nibble 8 instantiation
RAM16X1D fifo0_bit32
( .DPO(fifo_80_data_out[0]),
.SPO( ),
.A0(fifo_80_wr_addr[0]),
.A1(fifo_80_wr_addr[1]),
.A2(fifo_80_wr_addr[2]),
.A3(fifo_80_wr_addr[3]),
.D(ddr_dq_in[32]),
.DPRA0(fifo_80_rd_addr[0]),
.DPRA1(fifo_80_rd_addr[1]),
.DPRA2(fifo_80_rd_addr[2]),
.DPRA3(fifo_80_rd_addr[3]),
.WCLK(dqs8_delayed_col0),
.WE(fifo_80_wr_en)
);
RAM16X1D fifo1_bit32
( .DPO(fifo_81_data_out[0]),
.SPO( ),
.A0(fifo_81_wr_addr[0]),
.A1(fifo_81_wr_addr[1]),
.A2(fifo_81_wr_addr[2]),
.A3(fifo_81_wr_addr[3]),
.D(ddr_dq_in[32]),
.DPRA0(fifo_81_rd_addr[0]),
.DPRA1(fifo_81_rd_addr[1]),
.DPRA2(fifo_81_rd_addr[2]),
.DPRA3(fifo_81_rd_addr[3]),
.WCLK(dqs8_delayed_col0_n),
.WE(fifo_81_wr_en)
);
RAM16X1D fifo0_bit33
( .DPO(fifo_80_data_out[1]),
.SPO( ),
.A0(fifo_80_wr_addr[0]),
.A1(fifo_80_wr_addr[1]),
.A2(fifo_80_wr_addr[2]),
.A3(fifo_80_wr_addr[3]),
.D(ddr_dq_in[33]),
.DPRA0(fifo_80_rd_addr[0]),
.DPRA1(fifo_80_rd_addr[1]),
.DPRA2(fifo_80_rd_addr[2]),
.DPRA3(fifo_80_rd_addr[3]),
.WCLK(dqs8_delayed_col0),
.WE(fifo_80_wr_en)
);
RAM16X1D fifo1_bit33
( .DPO(fifo_81_data_out[1]),
.SPO( ),
.A0(fifo_81_wr_addr[0]),
.A1(fifo_81_wr_addr[1]),
.A2(fifo_81_wr_addr[2]),
.A3(fifo_81_wr_addr[3]),
.D(ddr_dq_in[33]),
.DPRA0(fifo_81_rd_addr[0]),
.DPRA1(fifo_81_rd_addr[1]),
.DPRA2(fifo_81_rd_addr[2]),
.DPRA3(fifo_81_rd_addr[3]),
.WCLK(dqs8_delayed_col0_n),
.WE(fifo_81_wr_en)
);
RAM16X1D fifo0_bit34
( .DPO(fifo_80_data_out[2]),
.SPO( ),
.A0(fifo_80_wr_addr[0]),
.A1(fifo_80_wr_addr[1]),
.A2(fifo_80_wr_addr[2]),
.A3(fifo_80_wr_addr[3]),
.D(ddr_dq_in[34]),
.DPRA0(fifo_80_rd_addr[0]),
.DPRA1(fifo_80_rd_addr[1]),
.DPRA2(fifo_80_rd_addr[2]),
.DPRA3(fifo_80_rd_addr[3]),
.WCLK(dqs8_delayed_col0),
.WE(fifo_80_wr_en)
);
RAM16X1D fifo1_bit34
( .DPO(fifo_81_data_out[2]),
.SPO( ),
.A0(fifo_81_wr_addr[0]),
.A1(fifo_81_wr_addr[1]),
.A2(fifo_81_wr_addr[2]),
.A3(fifo_81_wr_addr[3]),
.D(ddr_dq_in[34]),
.DPRA0(fifo_81_rd_addr[0]),
.DPRA1(fifo_81_rd_addr[1]),
.DPRA2(fifo_81_rd_addr[2]),
.DPRA3(fifo_81_rd_addr[3]),
.WCLK(dqs8_delayed_col0_n),
.WE(fifo_81_wr_en)
);
RAM16X1D fifo0_bit35
( .DPO(fifo_80_data_out[3]),
.SPO( ),
.A0(fifo_80_wr_addr[0]),
.A1(fifo_80_wr_addr[1]),
.A2(fifo_80_wr_addr[2]),
.A3(fifo_80_wr_addr[3]),
.D(ddr_dq_in[35]),
.DPRA0(fifo_80_rd_addr[0]),
.DPRA1(fifo_80_rd_addr[1]),
.DPRA2(fifo_80_rd_addr[2]),
.DPRA3(fifo_80_rd_addr[3]),
.WCLK(dqs8_delayed_col0),
.WE(fifo_80_wr_en)
);
RAM16X1D fifo1_bit35
( .DPO(fifo_81_data_out[3]),
.SPO( ),
.A0(fifo_81_wr_addr[0]),
.A1(fifo_81_wr_addr[1]),
.A2(fifo_81_wr_addr[2]),
.A3(fifo_81_wr_addr[3]),
.D(ddr_dq_in[35]),
.DPRA0(fifo_81_rd_addr[0]),
.DPRA1(fifo_81_rd_addr[1]),
.DPRA2(fifo_81_rd_addr[2]),
.DPRA3(fifo_81_rd_addr[3]),
.WCLK(dqs8_delayed_col0_n),
.WE(fifo_81_wr_en)
);
//- Nibble9 instantiation
RAM16X1D fifo0_bit36
( .DPO(fifo_90_data_out[0]),
.SPO( ),
.A0(fifo_90_wr_addr[0]),
.A1(fifo_90_wr_addr[1]),
.A2(fifo_90_wr_addr[2]),
.A3(fifo_90_wr_addr[3]),
.D(ddr_dq_in[36]),
.DPRA0(fifo_90_rd_addr[0]),
.DPRA1(fifo_90_rd_addr[1]),
.DPRA2(fifo_90_rd_addr[2]),
.DPRA3(fifo_90_rd_addr[3]),
.WCLK(dqs9_delayed_col0),
.WE(fifo_90_wr_en)
);
RAM16X1D fifo1_bit36
( .DPO(fifo_91_data_out[0]),
.SPO( ),
.A0(fifo_91_wr_addr[0]),
.A1(fifo_91_wr_addr[1]),
.A2(fifo_91_wr_addr[2]),
.A3(fifo_91_wr_addr[3]),
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