📄 data_read_48bit.v
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.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit14
( .DPO(fifo_30_data_out[2]),
.SPO( ),
.A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[14]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col0),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit14
( .DPO(fifo_31_data_out[2]),
.SPO( ),
.A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[14]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
RAM16X1D fifo0_bit15
( .DPO(fifo_30_data_out[3]),
.SPO( ),
.A0(fifo_30_wr_addr[0]),
.A1(fifo_30_wr_addr[1]),
.A2(fifo_30_wr_addr[2]),
.A3(fifo_30_wr_addr[3]),
.D(ddr_dq_in[15]),
.DPRA0(fifo_30_rd_addr[0]),
.DPRA1(fifo_30_rd_addr[1]),
.DPRA2(fifo_30_rd_addr[2]),
.DPRA3(fifo_30_rd_addr[3]),
.WCLK(dqs3_delayed_col0),
.WE(fifo_30_wr_en)
);
RAM16X1D fifo1_bit15
( .DPO(fifo_31_data_out[3]),
.SPO( ),
.A0(fifo_31_wr_addr[0]),
.A1(fifo_31_wr_addr[1]),
.A2(fifo_31_wr_addr[2]),
.A3(fifo_31_wr_addr[3]),
.D(ddr_dq_in[15]),
.DPRA0(fifo_31_rd_addr[0]),
.DPRA1(fifo_31_rd_addr[1]),
.DPRA2(fifo_31_rd_addr[2]),
.DPRA3(fifo_31_rd_addr[3]),
.WCLK(dqs3_delayed_col0_n),
.WE(fifo_31_wr_en)
);
// Nibble 4 Fifo instantiation
RAM16X1D fifo0_bit16
( .DPO(fifo_40_data_out[0]),
.SPO( ),
.A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[16]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit16
( .DPO(fifo_41_data_out[0]),
.SPO( ),
.A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[16]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit17
( .DPO(fifo_40_data_out[1]),
.SPO( ),
.A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[17]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit17
( .DPO(fifo_41_data_out[1]),
.SPO( ),
.A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[17]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit18
( .DPO(fifo_40_data_out[2]),
.SPO( ),
.A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[18]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit18
( .DPO(fifo_41_data_out[2]),
.SPO( ),
.A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[18]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
RAM16X1D fifo0_bit19
( .DPO(fifo_40_data_out[3]),
.SPO( ),
.A0(fifo_40_wr_addr[0]),
.A1(fifo_40_wr_addr[1]),
.A2(fifo_40_wr_addr[2]),
.A3(fifo_40_wr_addr[3]),
.D(ddr_dq_in[19]),
.DPRA0(fifo_40_rd_addr[0]),
.DPRA1(fifo_40_rd_addr[1]),
.DPRA2(fifo_40_rd_addr[2]),
.DPRA3(fifo_40_rd_addr[3]),
.WCLK(dqs4_delayed_col0),
.WE(fifo_40_wr_en)
);
RAM16X1D fifo1_bit19
( .DPO(fifo_41_data_out[3]),
.SPO( ),
.A0(fifo_41_wr_addr[0]),
.A1(fifo_41_wr_addr[1]),
.A2(fifo_41_wr_addr[2]),
.A3(fifo_41_wr_addr[3]),
.D(ddr_dq_in[19]),
.DPRA0(fifo_41_rd_addr[0]),
.DPRA1(fifo_41_rd_addr[1]),
.DPRA2(fifo_41_rd_addr[2]),
.DPRA3(fifo_41_rd_addr[3]),
.WCLK(dqs4_delayed_col0_n),
.WE(fifo_41_wr_en)
);
//- Nibble5 instantiation
RAM16X1D fifo0_bit20
( .DPO(fifo_50_data_out[0]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[20]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit20
( .DPO(fifo_51_data_out[0]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[20]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
RAM16X1D fifo0_bit21
( .DPO(fifo_50_data_out[1]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[21]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit21
( .DPO(fifo_51_data_out[1]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[21]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
RAM16X1D fifo0_bit22
( .DPO(fifo_50_data_out[2]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[22]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit22
( .DPO(fifo_51_data_out[2]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[22]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
RAM16X1D fifo0_bit23
( .DPO(fifo_50_data_out[3]),
.SPO( ),
.A0(fifo_50_wr_addr[0]),
.A1(fifo_50_wr_addr[1]),
.A2(fifo_50_wr_addr[2]),
.A3(fifo_50_wr_addr[3]),
.D(ddr_dq_in[23]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK(dqs5_delayed_col0),
.WE(fifo_50_wr_en)
);
RAM16X1D fifo1_bit23
( .DPO(fifo_51_data_out[3]),
.SPO( ),
.A0(fifo_51_wr_addr[0]),
.A1(fifo_51_wr_addr[1]),
.A2(fifo_51_wr_addr[2]),
.A3(fifo_51_wr_addr[3]),
.D(ddr_dq_in[23]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK(dqs5_delayed_col0_n),
.WE(fifo_51_wr_en)
);
//Nibble 6 Fifo Instantiation
RAM16X1D fifo0_bit24
( .DPO(fifo_60_data_out[0]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[24]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK(dqs6_delayed_col0),
.WE(fifo_60_wr_en)
);
RAM16X1D fifo1_bit24
( .DPO(fifo_61_data_out[0]),
.SPO( ),
.A0(fifo_61_wr_addr[0]),
.A1(fifo_61_wr_addr[1]),
.A2(fifo_61_wr_addr[2]),
.A3(fifo_61_wr_addr[3]),
.D(ddr_dq_in[24]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK(dqs6_delayed_col0_n),
.WE(fifo_61_wr_en)
);
RAM16X1D fifo0_bit25
( .DPO(fifo_60_data_out[1]),
.SPO( ),
.A0(fifo_60_wr_addr[0]),
.A1(fifo_60_wr_addr[1]),
.A2(fifo_60_wr_addr[2]),
.A3(fifo_60_wr_addr[3]),
.D(ddr_dq_in[25]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
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