data_path_48bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
`include "parameters_48bit.v"
module    data_path_48bit   ( 

     user_input_data,    
     user_data_mask,	
     clk,                
     clk90,              
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
     reset,              
     reset90,            
     reset180,           
     reset270,           
     write_enable,       
     rst_dqs_div_in,     
     delay_sel,          
     dqs_int_delay_in0,  
     dqs_int_delay_in1,       
     dqs_int_delay_in2,  
     dqs_int_delay_in3,            
     dqs_int_delay_in4,                 
     dqs_int_delay_in5,                      
     dqs_int_delay_in6,                           
     dqs_int_delay_in7,                           
     dqs_int_delay_in8,  
     dqs_int_delay_in9,  
     dqs_int_delay_in10,       
     dqs_int_delay_in11,  
     dq,                 
     u_data_val,         
     user_output_data,   
     write_en_val,       
     reset90_r_val,     
     data_mask_f,       
     data_mask_r,        
     write_data_falling, 
     write_data_rising  
     );

input     [95:0]user_input_data;
input     [((`mask_width)-1):0]  user_data_mask;   
input     clk;                
input     clk90;              
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
input     reset;              
input     reset90;            
input     reset180;           
input     reset270;           
input     write_enable;       
input     rst_dqs_div_in;     
input     [4:0]delay_sel;     
input     dqs_int_delay_in0;  
input     dqs_int_delay_in1;  
input     dqs_int_delay_in2;  
input     dqs_int_delay_in3;  
input     dqs_int_delay_in4;  
input     dqs_int_delay_in5;  
input     dqs_int_delay_in6;  
input     dqs_int_delay_in7;  
input     dqs_int_delay_in8;  
input     dqs_int_delay_in9;  
input     dqs_int_delay_in10;  
input     dqs_int_delay_in11;  
input     [47:0]dq;           
output     u_data_val;        
output     [95:0]user_output_data;  
output     write_en_val;      
output     reset90_r_val;     
output     [((`mask_width/2)-1):0] data_mask_f;        
output     [((`mask_width/2)-1):0] data_mask_r;       
output     [47:0]write_data_falling;
output     [47:0]write_data_rising;

wire reset_r;   
wire reset90_r; 
wire reset180_r;
wire reset270_r;
                                 
 wire [3:0]fifo_00_rd_addr;
 wire [3:0]fifo_01_rd_addr;
 wire [3:0]fifo_10_rd_addr;
 wire [3:0]fifo_11_rd_addr;
 wire [3:0]fifo_20_rd_addr;
 wire [3:0]fifo_21_rd_addr;
 wire [3:0]fifo_30_rd_addr;
 wire [3:0]fifo_31_rd_addr;
 wire [3:0]fifo_40_rd_addr;
 wire [3:0]fifo_41_rd_addr;
 wire [3:0]fifo_50_rd_addr;
 wire [3:0]fifo_51_rd_addr;
 wire [3:0]fifo_60_rd_addr;
 wire [3:0]fifo_61_rd_addr;
 wire [3:0]fifo_70_rd_addr;
 wire [3:0]fifo_71_rd_addr;  
 wire [3:0]fifo_80_rd_addr;
 wire [3:0]fifo_81_rd_addr;  
 wire [3:0]fifo_90_rd_addr;
 wire [3:0]fifo_91_rd_addr;  
 wire [3:0]fifo_100_rd_addr;
 wire [3:0]fifo_101_rd_addr;  
 wire [3:0]fifo_110_rd_addr;
 wire [3:0]fifo_111_rd_addr;  
                         
 wire read_valid_data_1;
 
 wire [3:0]fifo_00_wr_addr;          
 wire [3:0]fifo_10_wr_addr;          
 wire [3:0]fifo_20_wr_addr;          
 wire [3:0]fifo_30_wr_addr;   
 wire [3:0]fifo_40_wr_addr;   
 wire [3:0]fifo_50_wr_addr;   
 wire [3:0]fifo_60_wr_addr;   
 wire [3:0]fifo_01_wr_addr;          
 wire [3:0]fifo_11_wr_addr;          
 wire [3:0]fifo_21_wr_addr;          
 wire [3:0]fifo_31_wr_addr;          
 wire [3:0]fifo_41_wr_addr;   
 wire [3:0]fifo_51_wr_addr;   
 wire [3:0]fifo_61_wr_addr;   
 wire [3:0]fifo_70_wr_addr;          
 wire [3:0]fifo_71_wr_addr;          
 wire [3:0]fifo_80_wr_addr;          
 wire [3:0]fifo_81_wr_addr;          
 wire [3:0]fifo_90_wr_addr;          
 wire [3:0]fifo_91_wr_addr;          
 wire [3:0]fifo_100_wr_addr;          
 wire [3:0]fifo_101_wr_addr;          
 wire [3:0]fifo_110_wr_addr;         
 wire [3:0]fifo_111_wr_addr;            

 wire fifo_00_wr_en;
 wire fifo_10_wr_en;
 wire fifo_20_wr_en;
 wire fifo_30_wr_en;
 wire fifo_40_wr_en;
 wire fifo_50_wr_en; 
 wire fifo_60_wr_en; 
 wire fifo_70_wr_en;
 wire fifo_80_wr_en;
 wire fifo_90_wr_en;
 wire fifo_100_wr_en;
 wire fifo_110_wr_en;

 wire fifo_01_wr_en;
 wire fifo_11_wr_en;
 wire fifo_21_wr_en;
 wire fifo_31_wr_en;
 wire fifo_41_wr_en;
 wire fifo_51_wr_en;
 wire fifo_61_wr_en; 
 wire fifo_71_wr_en;
 wire fifo_81_wr_en;
 wire fifo_91_wr_en;
 wire fifo_101_wr_en;
 wire fifo_111_wr_en;
 
 wire dqs0_delayed_col0;
 wire dqs1_delayed_col0;
 wire dqs2_delayed_col0;
 wire dqs3_delayed_col0;
 wire dqs4_delayed_col0;
 wire dqs5_delayed_col0; 
 wire dqs6_delayed_col0;  
 wire dqs7_delayed_col0;
 wire dqs8_delayed_col0;
 wire dqs9_delayed_col0;
 wire dqs10_delayed_col0;
 wire dqs11_delayed_col0;

 wire dqs0_delayed_col0_n;
 wire dqs1_delayed_col0_n;
 wire dqs2_delayed_col0_n;
 wire dqs3_delayed_col0_n;
 wire dqs4_delayed_col0_n;
 wire dqs5_delayed_col0_n;
 wire dqs6_delayed_col0_n;
 wire dqs7_delayed_col0_n;
 wire dqs8_delayed_col0_n;
 wire dqs9_delayed_col0_n;
 wire dqs10_delayed_col0_n;
 wire dqs11_delayed_col0_n;
 
assign  reset90_r_val = reset90_r;


data_read_48bit	data_read0	( 

           .clk        (clk),          
           .clk90               (clk90),
           .reset90_r           (reset90_r),
           .reset270_r          (reset270_r),
	   .ddr_dq_in           (dq),
           .read_valid_data_1   (read_valid_data_1),
           
   	    .fifo_00_wr_en		     (fifo_00_wr_en),
   	    .fifo_10_wr_en		     (fifo_10_wr_en), 
    	    .fifo_20_wr_en		     (fifo_20_wr_en),
   	    .fifo_30_wr_en		     (fifo_30_wr_en),   	      	    
  	    .fifo_40_wr_en		     (fifo_40_wr_en),   	      	       	    
  	    .fifo_50_wr_en		     (fifo_50_wr_en),   	      	       	      	    
  	    .fifo_60_wr_en		     (fifo_60_wr_en),   	      	       	      	      	   
	    .fifo_70_wr_en		     (fifo_70_wr_en),
	    .fifo_80_wr_en		     (fifo_80_wr_en),
	    .fifo_90_wr_en		     (fifo_90_wr_en),
	    .fifo_100_wr_en		     (fifo_100_wr_en),
	    .fifo_110_wr_en		     (fifo_110_wr_en),
  
   	    .fifo_01_wr_en		     (fifo_01_wr_en),
   	    .fifo_11_wr_en		     (fifo_11_wr_en),	    
   	    .fifo_21_wr_en		     (fifo_21_wr_en),
   	    .fifo_31_wr_en		     (fifo_31_wr_en),    	    
   	    .fifo_41_wr_en		     (fifo_41_wr_en),    	       	    
   	    .fifo_51_wr_en		     (fifo_51_wr_en),    	       	       	    
   	    .fifo_61_wr_en		     (fifo_61_wr_en),    	       	       	       	    
	    .fifo_71_wr_en		     (fifo_71_wr_en),
	    .fifo_81_wr_en		     (fifo_81_wr_en),	    
	    .fifo_91_wr_en		     (fifo_91_wr_en),	    
	    .fifo_101_wr_en		     (fifo_101_wr_en),
	    .fifo_111_wr_en		     (fifo_111_wr_en),
	 
	    .fifo_00_wr_addr     (fifo_00_wr_addr),
	    .fifo_10_wr_addr     (fifo_10_wr_addr),	
	    .fifo_20_wr_addr     (fifo_20_wr_addr),
	    .fifo_30_wr_addr     (fifo_30_wr_addr),	    
	    .fifo_40_wr_addr     (fifo_40_wr_addr),	    	        
	    .fifo_50_wr_addr     (fifo_50_wr_addr),	    	        	    
	    .fifo_60_wr_addr     (fifo_60_wr_addr),	    	        	    	    
            .fifo_70_wr_addr     (fifo_70_wr_addr),
            .fifo_80_wr_addr     (fifo_80_wr_addr),
            .fifo_90_wr_addr     (fifo_90_wr_addr),
	    .fifo_100_wr_addr     (fifo_100_wr_addr),