📄 data_path_iobs_48bit.v
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`timescale 1ns/100ps
`include "parameters_48bit.v"
module data_path_iobs_48bit (
clk,
clk90,
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
reset90_r,
dqs_reset,
dqs_enable,
ddr_dqs,
ddr_dq,
write_data_falling,
write_data_rising,
write_en_val,
data_mask_f,
data_mask_r,
dqs_int_delay_in0,
dqs_int_delay_in1,
dqs_int_delay_in2,
dqs_int_delay_in3,
dqs_int_delay_in4,
dqs_int_delay_in5,
ddr_dq_val,
ddr_dm
);
input clk;
input clk90;
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
input reset90_r;
input dqs_reset;
input dqs_enable;
inout [5:0]ddr_dqs;
inout [47:0]ddr_dq;
input [47:0]write_data_falling;
input [47:0]write_data_rising;
input write_en_val;
input [5:0]data_mask_f;
input [5:0]data_mask_r;
output dqs_int_delay_in0;
output dqs_int_delay_in1;
output dqs_int_delay_in2;
output dqs_int_delay_in3;
output dqs_int_delay_in4;
output dqs_int_delay_in5;
output [47:0]ddr_dq_val;
output [5:0]ddr_dm;
//SYN_REMOVECOMMENT wire clk270 /* synthesis syn_keep =1 */;
//SYN_REMOVECOMMENT wire clk180 /* synthesis syn_keep =1 */;
wire [47:0]ddr_dq_in;
//SYN_REMOVECOMMENT assign clk270 = ~ clk90;
//SYN_REMOVECOMMENT assign clk180 = ~ clk;
assign ddr_dq_val = ddr_dq_in;
ddr1_dm_48bit ddr1_dm0 (
.ddr_dm (ddr_dm),
.mask_falling (data_mask_f),
.mask_rising (data_mask_r),
.clk90 (clk90),
.clk270 (clk270)
);
//***********************************************************************
// Read Data Capture Module Instantiations
//***********************************************************************
// DQS IOB instantiations
//***********************************************************************
ddr_dqs_iob ddr_dqs_iob0 (
.clk (clk),
.clk180 (clk180),
.ddr_dqs_reset (dqs_reset),
.ddr_dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs[0]),
.dqs (dqs_int_delay_in0)
);
ddr_dqs_iob ddr_dqs_iob1 (
.clk (clk),
.clk180 (clk180),
.ddr_dqs_reset (dqs_reset),
.ddr_dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs[1]),
.dqs (dqs_int_delay_in1)
);
ddr_dqs_iob ddr_dqs_iob2 (
.clk (clk),
.clk180 (clk180),
.ddr_dqs_reset (dqs_reset),
.ddr_dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs[2]),
.dqs (dqs_int_delay_in2)
);
ddr_dqs_iob ddr_dqs_iob3 (
.clk (clk),
.clk180 (clk180),
.ddr_dqs_reset (dqs_reset),
.ddr_dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs[3]),
.dqs (dqs_int_delay_in3)
);
ddr_dqs_iob ddr_dqs_iob4 (
.clk (clk),
.clk180 (clk180),
.ddr_dqs_reset (dqs_reset),
.ddr_dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs[4]),
.dqs (dqs_int_delay_in4)
);
ddr_dqs_iob ddr_dqs_iob5 (
.clk (clk),
.clk180 (clk180),
.ddr_dqs_reset (dqs_reset),
.ddr_dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs[5]),
.dqs (dqs_int_delay_in5)
);
//******************************************************************************************************************************
// DDR Data bit instantiations (72-bits)
//******************************************************************************************************************************
ddr_dq_iob ddr_dq_iob0
(
.ddr_dq_inout (ddr_dq[0]),
.write_data_falling (write_data_falling[0]),
.write_data_rising (write_data_rising[0]),
.read_data_in (ddr_dq_in[0]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob1
(
.ddr_dq_inout (ddr_dq[1]),
.write_data_falling (write_data_falling[1]),
.write_data_rising (write_data_rising[1]),
.read_data_in (ddr_dq_in[1]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob2
(
.ddr_dq_inout (ddr_dq[2]),
.write_data_falling (write_data_falling[2]),
.write_data_rising (write_data_rising[2]),
.read_data_in (ddr_dq_in[2]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob3
(
.ddr_dq_inout (ddr_dq[3]),
.write_data_falling (write_data_falling[3]),
.write_data_rising (write_data_rising[3]),
.read_data_in (ddr_dq_in[3]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob4
(
.ddr_dq_inout (ddr_dq[4]),
.write_data_falling (write_data_falling[4]),
.write_data_rising (write_data_rising[4]),
.read_data_in (ddr_dq_in[4]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob5
(
.ddr_dq_inout (ddr_dq[5]),
.write_data_falling (write_data_falling[5]),
.write_data_rising (write_data_rising[5]),
.read_data_in (ddr_dq_in[5]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob6
(
.ddr_dq_inout (ddr_dq[6]),
.write_data_falling (write_data_falling[6]),
.write_data_rising (write_data_rising[6]),
.read_data_in (ddr_dq_in[6]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob7
(
.ddr_dq_inout (ddr_dq[7]),
.write_data_falling (write_data_falling[7]),
.write_data_rising (write_data_rising[7]),
.read_data_in (ddr_dq_in[7]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob8
(
.ddr_dq_inout (ddr_dq[8]),
.write_data_falling (write_data_falling[8]),
.write_data_rising (write_data_rising[8]),
.read_data_in (ddr_dq_in[8]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob9
(
.ddr_dq_inout (ddr_dq[9]),
.write_data_falling (write_data_falling[9]),
.write_data_rising (write_data_rising[9]),
.read_data_in (ddr_dq_in[9]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob10
(
.ddr_dq_inout (ddr_dq[10]),
.write_data_falling (write_data_falling[10]),
.write_data_rising (write_data_rising[10]),
.read_data_in (ddr_dq_in[10]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob11
(
.ddr_dq_inout (ddr_dq[11]),
.write_data_falling (write_data_falling[11]),
.write_data_rising (write_data_rising[11]),
.read_data_in (ddr_dq_in[11]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob12
(
.ddr_dq_inout (ddr_dq[12]),
.write_data_falling (write_data_falling[12]),
.write_data_rising (write_data_rising[12]),
.read_data_in (ddr_dq_in[12]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob13
(
.ddr_dq_inout (ddr_dq[13]),
.write_data_falling (write_data_falling[13]),
.write_data_rising (write_data_rising[13]),
.read_data_in (ddr_dq_in[13]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob14
(
.ddr_dq_inout (ddr_dq[14]),
.write_data_falling (write_data_falling[14]),
.write_data_rising (write_data_rising[14]),
.read_data_in (ddr_dq_in[14]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob15
(
.ddr_dq_inout (ddr_dq[15]),
.write_data_falling (write_data_falling[15]),
.write_data_rising (write_data_rising[15]),
.read_data_in (ddr_dq_in[15]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob16
(
.ddr_dq_inout (ddr_dq[16]),
.write_data_falling (write_data_falling[16]),
.write_data_rising (write_data_rising[16]),
.read_data_in (ddr_dq_in[16]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob17
(
.ddr_dq_inout (ddr_dq[17]),
.write_data_falling (write_data_falling[17]),
.write_data_rising (write_data_rising[17]),
.read_data_in (ddr_dq_in[17]),
.clk90 (clk90),
.clk270 (clk270),
.write_en_val (write_en_val),
.reset (reset90_r)
);
ddr_dq_iob ddr_dq_iob18
(
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