infrastructure_iobs_72bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

  `timescale 1ns/100ps
module    infrastructure_iobs_72bit   ( 

      clk0,              
      clk90,             
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
      ddr1_clk0,         
      ddr1_clk0b,        
      ddr1_clk1,         
      ddr1_clk1b,        
      ddr1_clk2,         
      ddr1_clk2b,        
      ddr1_clk3,         
      ddr1_clk3b,        
      ddr1_clk4,         
      ddr1_clk4b,        
      ddr1_clk5,         
      ddr1_clk5b,        
      ddr1_clk6,         
      ddr1_clk6b,        
      ddr1_clk7,         
      ddr1_clk7b,        
      ddr1_clk8,         
      ddr1_clk8b,        
      ddr1_clk9,         
      ddr1_clk9b,        
      ddr1_clk10,         
      ddr1_clk10b,        
      ddr1_clk11,         
      ddr1_clk11b,        
      ddr1_clk12,         
      ddr1_clk12b,        
      ddr1_clk13,         
      ddr1_clk13b,        
      ddr1_clk14,         
      ddr1_clk14b,        
      ddr1_clk15,         
      ddr1_clk15b,        
      ddr1_clk16,         
      ddr1_clk16b,        
      ddr1_clk17,         
      ddr1_clk17b        
      );
      
input      clk0;              
input      clk90;             
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
output      ddr1_clk0;         
output      ddr1_clk0b;        
output      ddr1_clk1;         
output      ddr1_clk1b;        
output      ddr1_clk2;         
output      ddr1_clk2b;        
output      ddr1_clk3;         
output      ddr1_clk3b;        
output      ddr1_clk4;         
output      ddr1_clk4b;        
output      ddr1_clk5;         
output      ddr1_clk5b;        
output      ddr1_clk6;         
output      ddr1_clk6b;        
output      ddr1_clk7;         
output      ddr1_clk7b;        
output      ddr1_clk8;         
output      ddr1_clk8b;        
output      ddr1_clk9;         
output      ddr1_clk9b;        
output      ddr1_clk10;         
output      ddr1_clk10b;        
output      ddr1_clk11;         
output      ddr1_clk11b;        
output      ddr1_clk12;         
output      ddr1_clk12b;        
output      ddr1_clk13;         
output      ddr1_clk13b;        
output      ddr1_clk14;         
output      ddr1_clk14b;        
output      ddr1_clk15;         
output      ddr1_clk15b;        
output      ddr1_clk16;         
output      ddr1_clk16b;        
output      ddr1_clk17;         
output      ddr1_clk17b;        
   
   
wire ddr1_clk0_q; 
wire ddr1_clk0b_q;
wire ddr1_clk1_q; 
wire ddr1_clk1b_q;
wire ddr1_clk2_q; 
wire ddr1_clk2b_q;
wire ddr1_clk3_q; 
wire ddr1_clk3b_q;
wire ddr1_clk4_q; 
wire ddr1_clk4b_q;
wire ddr1_clk5_q;          
wire ddr1_clk5b_q;         
wire ddr1_clk6_q;          
wire ddr1_clk6b_q;         
wire ddr1_clk7_q;          
wire ddr1_clk7b_q;         
wire ddr1_clk8_q;          
wire ddr1_clk8b_q;         
wire ddr1_clk9_q;          
wire ddr1_clk9b_q;         
wire ddr1_clk10_q;          
wire ddr1_clk10b_q;         
wire ddr1_clk11_q;          
wire ddr1_clk11b_q;         
wire ddr1_clk12_q;          
wire ddr1_clk12b_q;         
wire ddr1_clk13_q;          
wire ddr1_clk13b_q;         
wire ddr1_clk14_q;          
wire ddr1_clk14b_q;         
wire vcc;   
wire gnd;   
//SYN_REMOVECOMMENT wire clk180;
//SYN_REMOVECOMMENT wire clk270;
   
   
//SYN_REMOVECOMMENT assign clk180 = ~ clk0;
//SYN_REMOVECOMMENT assign  clk270 = ~ clk90;
assign  gnd = 1'b0;
assign  vcc = 1'b1;   





//----  Component instantiations  ----

//--- ***********************************
//---  DCI Input buffer for System clock

//---- ***********************************************************
//----     Output DDR generation
//----     This includes instantiation of the output DDR flip flop
//----     for ddr clk's and dimm clk's
//---- ***********************************************************


FDDRRSE DDRCLK0_INST    ( .Q  (ddr1_clk0_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK0B_INST    ( .Q  (ddr1_clk0b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
                                   
FDDRRSE DDRCLK1_INST    ( .Q  (ddr1_clk1_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK1B_INST    ( .Q  (ddr1_clk1b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK2_INST    ( .Q  (ddr1_clk2_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK2B_INST    ( .Q  (ddr1_clk2b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );


FDDRRSE DDRCLK3_INST    ( .Q  (ddr1_clk3_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK3B_INST    ( .Q  (ddr1_clk3b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK4_INST    ( .Q  (ddr1_clk4_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK4B_INST    ( .Q  (ddr1_clk4b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK5_INST    ( .Q  (ddr1_clk5_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK5B_INST    ( .Q  (ddr1_clk5b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK6_INST    ( .Q  (ddr1_clk6_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );

FDDRRSE DDRCLK6B_INST    ( .Q  (ddr1_clk6b_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
                                   
FDDRRSE DDRCLK7_INST    ( .Q  (ddr1_clk7_q), 
                          .C0 (clk0), 
                          .C1 (clk180), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd),