📄 ddr1_top_72bit.v
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wire [((`mask_width/2)-1):0] data_mask_r;
wire [71:0]write_data_falling;
wire [71:0]write_data_rising;
wire ddr_rasb_cntrl;
wire ddr_casb_cntrl;
wire ddr_web_cntrl;
wire [`bank_address-1:0]ddr_ba_cntrl;
wire [`row_address-1:0]ddr_address_cntrl;
wire ddr_cke_cntrl;
wire ddr_csb_cntrl;
wire rst_dqs_div_int;
controller1_72bit controller0 (
.auto_ref_req (auto_ref_req),
.wait_200us(wait_200us),
.dip1 ( dip1),
.dip3 ( dip3),
.clk (clk_int),
//XST_REMOVECOMMENT .clk180 (clk180),
.rst0 (sys_rst),
.rst180 (sys_rst180),
.address (user_input_address),
.bank_address (user_bank_address),
.config_register (user_config_register),
.command_register (user_command_register),
.burst_done (burst_done),
.ddr_rasb_cntrl (ddr_rasb_cntrl),
.ddr_casb_cntrl (ddr_casb_cntrl),
.ddr_web_cntrl (ddr_web_cntrl),
.ddr_ba_cntrl (ddr_ba_cntrl),
.ddr_address_cntrl (ddr_address_cntrl),
.ddr_cke_cntrl (ddr_cke_cntrl),
.ddr_csb_cntrl (ddr_csb_cntrl),
.dqs_enable (dqs_enable),
.dqs_reset (dqs_reset),
.write_enable (write_enable),
.rst_calib (rst_calib),
.rst_dqs_div_int (rst_dqs_div_int),
.cmd_ack (user_cmd_ack),
.init (init_val),
.ar_done (ar_done)
);
data_path_72bit data_path0 (
.user_input_data (user_input_data),
.user_data_mask (user_data_mask),
.clk (clk_int),
.clk90 (clk90_int),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.reset (sys_rst),
.reset90 (sys_rst90),
.reset180 (sys_rst180),
.reset270 (sys_rst270),
.write_enable (write_enable),
.rst_dqs_div_in (dqs_div_rst),
.delay_sel (delay_sel),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.dqs_int_delay_in4 (dqs_int_delay_in4),
.dqs_int_delay_in5 (dqs_int_delay_in5),
.dqs_int_delay_in6 (dqs_int_delay_in6),
.dqs_int_delay_in7 (dqs_int_delay_in7),
.dqs_int_delay_in8 (dqs_int_delay_in8),
.dqs_int_delay_in9 (dqs_int_delay_in9),
.dqs_int_delay_in10 (dqs_int_delay_in10),
.dqs_int_delay_in11 (dqs_int_delay_in11),
.dqs_int_delay_in12 (dqs_int_delay_in12),
.dqs_int_delay_in13 (dqs_int_delay_in13),
.dqs_int_delay_in14 (dqs_int_delay_in14),
.dqs_int_delay_in15 (dqs_int_delay_in15),
.dqs_int_delay_in16 (dqs_int_delay_in16),
.dqs_int_delay_in17 (dqs_int_delay_in17),
.dq (dq),
.u_data_val (user_data_valid),
.user_output_data (user_output_data),
.write_en_val (write_en_val),
.reset90_r_val (reset90_r),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r),
.write_data_falling (write_data_falling),
.write_data_rising (write_data_rising)
);
infrastructure infrastructure0
(
.sys_rst(sys_rst),
.clk_int(clk_int),
.rst_calib1(rst_calib),
.delay_sel_val(delay_sel_val),
.delay_sel_val1_val(delay_sel)
);
iobs1_72bit iobs0
(
.clk (clk_int),
.clk90 (clk90_int),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.ddr_rasb_cntrl (ddr_rasb_cntrl),
.ddr_casb_cntrl (ddr_casb_cntrl),
.ddr_web_cntrl (ddr_web_cntrl),
.ddr_cke_cntrl (ddr_cke_cntrl),
.ddr_csb_cntrl (ddr_csb_cntrl),
.ddr_address_cntrl (ddr_address_cntrl),
.ddr_ba_cntrl (ddr_ba_cntrl),
.rst_dqs_div_int (rst_dqs_div_int),
.dqs_reset (dqs_reset),
.dqs_enable (dqs_enable),
.ddr_dqs (ddr_dqs),
.ddr_dq (ddr_dq),
.write_data_falling(write_data_falling),
.write_data_rising (write_data_rising),
.write_en_val (write_en_val),
.reset90_r (reset90_r),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r),
.ddr1_clk0 (ddr1_clk0),
.ddr1_clk0b (ddr1_clk0b),
.ddr1_clk1 (ddr1_clk1),
.ddr1_clk1b (ddr1_clk1b),
.ddr1_clk2 (ddr1_clk2),
.ddr1_clk2b (ddr1_clk2b),
.ddr1_clk3 (ddr1_clk3),
.ddr1_clk3b (ddr1_clk3b),
.ddr1_clk4 (ddr1_clk4),
.ddr1_clk4b (ddr1_clk4b),
.ddr1_clk5 (ddr1_clk5),
.ddr1_clk5b (ddr1_clk5b),
.ddr1_clk6 (ddr1_clk6),
.ddr1_clk6b (ddr1_clk6b),
.ddr1_clk7 (ddr1_clk7),
.ddr1_clk7b (ddr1_clk7b),
.ddr1_clk8 (ddr1_clk8),
.ddr1_clk8b (ddr1_clk8b),
.ddr1_clk9 (ddr1_clk9),
.ddr1_clk9b (ddr1_clk9b),
.ddr1_clk10 (ddr1_clk10),
.ddr1_clk10b (ddr1_clk10b),
.ddr1_clk11 (ddr1_clk11),
.ddr1_clk11b (ddr1_clk11b),
.ddr1_clk12 (ddr1_clk12),
.ddr1_clk12b (ddr1_clk12b),
.ddr1_clk13 (ddr1_clk13),
.ddr1_clk13b (ddr1_clk13b),
.ddr1_clk14 (ddr1_clk14),
.ddr1_clk14b (ddr1_clk14b),
.ddr1_clk15 (ddr1_clk15),
.ddr1_clk15b (ddr1_clk15b),
.ddr1_clk16 (ddr1_clk16),
.ddr1_clk16b (ddr1_clk16b),
.ddr1_clk17 (ddr1_clk17),
.ddr1_clk17b (ddr1_clk17b),
.ddr_rasb (ddr_rasb),
.ddr_casb (ddr_casb),
.ddr_web (ddr_web),
.ddr_ba (ddr_ba),
.ddr_address (ddr_address),
.ddr_cke (ddr_cke),
.ddr_csb (ddr_csb),
.rst_dqs_div (dqs_div_rst),
.rst_dqs_div_in (rst_dqs_div_in),
.rst_dqs_div_out ( rst_dqs_div_out),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.dqs_int_delay_in4 (dqs_int_delay_in4),
.dqs_int_delay_in5 (dqs_int_delay_in5),
.dqs_int_delay_in6 (dqs_int_delay_in6),
.dqs_int_delay_in7 (dqs_int_delay_in7),
.dqs_int_delay_in8 (dqs_int_delay_in8),
.dqs_int_delay_in9 (dqs_int_delay_in9),
.dqs_int_delay_in10 (dqs_int_delay_in10),
.dqs_int_delay_in11 (dqs_int_delay_in11),
.dqs_int_delay_in12 (dqs_int_delay_in12),
.dqs_int_delay_in13 (dqs_int_delay_in13),
.dqs_int_delay_in14 (dqs_int_delay_in14),
.dqs_int_delay_in15 (dqs_int_delay_in15),
.dqs_int_delay_in16 (dqs_int_delay_in16),
.dqs_int_delay_in17 (dqs_int_delay_in17),
.dq (dq),
.ddr_dm (ddr_dm)
);
endmodule
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