ddr1_top_72bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

`timescale 1ns/100ps
`include "parameters_72bit.v"

module    ddr1_top_72bit   ( 

     dip1,                  
     dip3,                  
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
       clk_int,
       clk90_int,
       delay_sel_val,
       sys_rst90,
       sys_rst180,
       sys_rst270,
       rst_dqs_div_in,
     rst_dqs_div_out,  					
     reset_in,              
     user_input_data,       
      user_data_mask,      
      user_output_data,      
     user_data_valid,      
     user_input_address,   
      user_bank_address,    
     user_config_register,  
     user_command_register, 
     user_cmd_ack,          
     burst_done,            
     init_val,              
     ar_done,               
     ddr_dqs,               
     ddr_dq,                
     ddr_cke,               
     ddr_csb,               
     ddr_rasb,              
     ddr_casb,              
     ddr_web,               
     ddr_dm,                
     ddr_ba,                
     ddr_address,           
auto_ref_req,  
wait_200us, 
     ddr1_clk0,             
     ddr1_clk0b,            
     ddr1_clk1,             
     ddr1_clk1b,            
     ddr1_clk2,             
     ddr1_clk2b,            
     ddr1_clk3,             
     ddr1_clk3b,            
     ddr1_clk4,             
     ddr1_clk4b,  
     ddr1_clk5,        
     ddr1_clk5b,
     ddr1_clk6,        
     ddr1_clk6b,
     ddr1_clk7,        
     ddr1_clk7b,
     ddr1_clk8,        
     ddr1_clk8b,
     ddr1_clk9,        
     ddr1_clk9b,
     ddr1_clk10,        
     ddr1_clk10b,       
     ddr1_clk11,        
     ddr1_clk11b,       
     ddr1_clk12,        
     ddr1_clk12b,       
     ddr1_clk13,        
     ddr1_clk13b,       
     ddr1_clk14,        
     ddr1_clk14b,
     ddr1_clk15,        
     ddr1_clk15b,
     ddr1_clk16,        
     ddr1_clk16b,
     ddr1_clk17,        
     ddr1_clk17b,
               
       sys_rst
     );
     
     
input     dip1;
 input     dip3;
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
 input     rst_dqs_div_in;
 output    rst_dqs_div_out;
input       clk_int;
input       clk90_int;
input       reset_in;
input      [4:0] delay_sel_val;
input       sys_rst;
input       sys_rst90;
input       sys_rst180;
input       sys_rst270;
input     [143:0]user_input_data;
input     [((`mask_width)-1):0] user_data_mask;

 output    [143:0]user_output_data;
output    user_data_valid;
input     [((`row_address + `column_address)-1):0]user_input_address; 
 input     [`bank_address-1:0]user_bank_address;   
 input     [9:0]user_config_register;
 input     [2:0]user_command_register;
 output    user_cmd_ack;          
input     burst_done;           
 output    init_val;        
output    ar_done;         
inout     [17:0]ddr_dqs;
inout     [71:0]ddr_dq;
output     ddr_cke;              
output     ddr_csb;              
output    auto_ref_req;  
input    wait_200us; 
output     ddr_rasb;             
output     ddr_casb;             
output     ddr_web;              
output     [((`mask_width/2)-1):0]  ddr_dm;           
output     [`bank_address-1:0]ddr_ba;           
output     [`row_address-1:0]ddr_address;     
output     ddr1_clk0;             
output     ddr1_clk0b;            
output     ddr1_clk1;             
output     ddr1_clk1b;            
output     ddr1_clk2;             
output     ddr1_clk2b;            
output     ddr1_clk3;             
output     ddr1_clk3b;            
output     ddr1_clk4;             
output     ddr1_clk4b;            
output     ddr1_clk5;       
output     ddr1_clk5b;  
output     ddr1_clk6;       
output     ddr1_clk6b;  
output     ddr1_clk7;       
output     ddr1_clk7b;
output     ddr1_clk8;       
output     ddr1_clk8b;
output     ddr1_clk9;       
output     ddr1_clk9b;
output     ddr1_clk10;       
output     ddr1_clk10b;  
output     ddr1_clk11;       
output     ddr1_clk11b;  
output     ddr1_clk12;       
output     ddr1_clk12b;
output     ddr1_clk13;       
output     ddr1_clk13b;
output     ddr1_clk14;       
output     ddr1_clk14b;
output     ddr1_clk15;       
output     ddr1_clk15b;
output     ddr1_clk16;       
output     ddr1_clk16b;
output     ddr1_clk17;       
output     ddr1_clk17b;

wire rst_calib;     
wire [4:0]delay_sel;
wire sys_rst;       
wire sys_rst90;     
wire sys_rst180;    
wire sys_rst270;    
wire clk_int;       
wire clk90_int;     
wire write_enable;      
wire dqs_div_rst;       
wire dqs_enable;        
wire dqs_reset;         
wire dqs_int_delay_in0; 
wire dqs_int_delay_in1; 
wire dqs_int_delay_in2; 
wire dqs_int_delay_in3; 
wire dqs_int_delay_in4; 
wire dqs_int_delay_in5; 
wire dqs_int_delay_in6; 
wire dqs_int_delay_in7; 
wire dqs_int_delay_in8; 
wire dqs_int_delay_in9;
wire dqs_int_delay_in10;  
wire dqs_int_delay_in11; 
wire dqs_int_delay_in12; 
wire dqs_int_delay_in13;
wire dqs_int_delay_in14; 
wire dqs_int_delay_in15; 
wire dqs_int_delay_in16; 
wire dqs_int_delay_in17; 
wire [71:0]dq; 
wire u_data_val;    
wire write_en_val; 
wire reset90_r;    
wire [((`mask_width/2)-1):0] data_mask_f;