data_read_72bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

   wire dqs0_delayed_col1_n;
   wire dqs1_delayed_col1_n;
   wire dqs2_delayed_col1_n;
   wire dqs3_delayed_col1_n;
   wire dqs4_delayed_col1_n;
   wire dqs5_delayed_col1_n;
   wire dqs6_delayed_col1_n;
   wire dqs7_delayed_col1_n;
   wire dqs8_delayed_col1_n;


   assign dqs0_delayed_col0_n = ~ dqs0_delayed_col0;
   assign dqs1_delayed_col0_n = ~ dqs1_delayed_col0;
   assign dqs2_delayed_col0_n = ~ dqs2_delayed_col0;
   assign dqs3_delayed_col0_n = ~ dqs3_delayed_col0;
   assign dqs4_delayed_col0_n = ~ dqs4_delayed_col0;
   assign dqs5_delayed_col0_n = ~ dqs5_delayed_col0;
   assign dqs6_delayed_col0_n = ~ dqs6_delayed_col0;
   assign dqs7_delayed_col0_n = ~ dqs7_delayed_col0;
   assign dqs8_delayed_col0_n = ~ dqs8_delayed_col0;

   assign dqs0_delayed_col1_n = ~ dqs0_delayed_col1;
   assign dqs1_delayed_col1_n = ~ dqs1_delayed_col1;
   assign dqs2_delayed_col1_n = ~ dqs2_delayed_col1;
   assign dqs3_delayed_col1_n = ~ dqs3_delayed_col1;
   assign dqs4_delayed_col1_n = ~ dqs4_delayed_col1;
   assign dqs5_delayed_col1_n = ~ dqs5_delayed_col1;
   assign dqs6_delayed_col1_n = ~ dqs6_delayed_col1;
   assign dqs7_delayed_col1_n = ~ dqs7_delayed_col1;
   assign dqs8_delayed_col1_n = ~ dqs8_delayed_col1;

   assign user_output_data    = first_sdr_data;
   assign fifo0_rd_addr_val   = fifo01_rd_addr;
   assign fifo1_rd_addr_val   = fifo00_rd_addr;


   
   always@(posedge clk90)begin
      if(reset90_r)begin
         fifo_00_data_out_r <= 8'd0;
         fifo_01_data_out_r <= 8'd0;
         fifo_10_data_out_r <= 8'd0;  // *** honey  
         fifo_11_data_out_r <= 8'd0;  // *** honey  
         fifo_20_data_out_r <= 8'd0;
         fifo_21_data_out_r <= 8'd0;
         fifo_30_data_out_r <= 8'd0;
         fifo_31_data_out_r <= 8'd0;
         fifo_40_data_out_r <= 8'd0;
         fifo_41_data_out_r <= 8'd0;
         fifo_50_data_out_r <= 8'd0;
         fifo_51_data_out_r <= 8'd0;
         fifo_60_data_out_r <= 8'd0;
         fifo_61_data_out_r <= 8'd0;
         fifo_70_data_out_r <= 8'd0;
         fifo_71_data_out_r <= 8'd0;
         fifo_80_data_out_r <= 8'd0;
         fifo_81_data_out_r <= 8'd0;


      end
      else 
      begin
         fifo_00_data_out_r <= fifo_00_data_out;
         fifo_01_data_out_r <= fifo_01_data_out;
         fifo_10_data_out_r <= fifo_10_data_out;
         fifo_11_data_out_r <= fifo_11_data_out;
         fifo_20_data_out_r <= fifo_20_data_out;
         fifo_21_data_out_r <= fifo_21_data_out;
         fifo_30_data_out_r <= fifo_30_data_out;
         fifo_31_data_out_r <= fifo_31_data_out;
         fifo_40_data_out_r <= fifo_40_data_out;
         fifo_41_data_out_r <= fifo_41_data_out;
         fifo_50_data_out_r <= fifo_50_data_out;
         fifo_51_data_out_r <= fifo_51_data_out;
         fifo_60_data_out_r <= fifo_60_data_out;
         fifo_61_data_out_r <= fifo_61_data_out;
         fifo_70_data_out_r <= fifo_70_data_out;
         fifo_71_data_out_r <= fifo_71_data_out; 
         fifo_80_data_out_r <= fifo_80_data_out;
         fifo_81_data_out_r <= fifo_81_data_out;

      end
   end

   always@(posedge clk90)begin
      if(reset90_r)begin
         fifo00_rd_addr_r <= 4'd0;              // *** honey   
         fifo01_rd_addr_r <= 4'd0;  
         fifo10_rd_addr_r <= 4'd0;
         fifo11_rd_addr_r <= 4'd0;
         fifo20_rd_addr_r <= 4'd0;
         fifo21_rd_addr_r <= 4'd0;
         fifo30_rd_addr_r <= 4'd0;
         fifo31_rd_addr_r <= 4'd0;
         fifo40_rd_addr_r <= 4'd0;
         fifo41_rd_addr_r <= 4'd0;
         fifo50_rd_addr_r <= 4'd0;
         fifo51_rd_addr_r <= 4'd0;
         fifo60_rd_addr_r <= 4'd0;
         fifo61_rd_addr_r <= 4'd0;
         fifo70_rd_addr_r <= 4'd0;
         fifo71_rd_addr_r <= 4'd0;
         fifo80_rd_addr_r <= 4'd0;
         fifo81_rd_addr_r <= 4'd0;
         fifop_rd_addr_r  <= 4'd0;
      end
      else begin
         fifo00_rd_addr_r <= fifo00_rd_addr;
         fifo01_rd_addr_r <= fifo00_rd_addr;
         fifo10_rd_addr_r <= fifo00_rd_addr;
         fifo11_rd_addr_r <= fifo00_rd_addr;
         fifo20_rd_addr_r <= fifo00_rd_addr;
         fifo21_rd_addr_r <= fifo00_rd_addr;
         fifo30_rd_addr_r <= fifo00_rd_addr;
         fifo31_rd_addr_r <= fifo00_rd_addr;
         fifo40_rd_addr_r <= fifo00_rd_addr;
         fifo41_rd_addr_r <= fifo00_rd_addr;
         fifo50_rd_addr_r <= fifo01_rd_addr;
         fifo51_rd_addr_r <= fifo01_rd_addr;
         fifo60_rd_addr_r <= fifo01_rd_addr;
         fifo61_rd_addr_r <= fifo01_rd_addr;
         fifo70_rd_addr_r <= fifo01_rd_addr;
         fifo71_rd_addr_r <= fifo01_rd_addr;
         fifo80_rd_addr_r <= fifo01_rd_addr;
         fifo81_rd_addr_r <= fifo01_rd_addr;
         fifop_rd_addr_r  <= fifo01_rd_addr; 
      end
   end


   always@(posedge clk90)begin
      if(reset90_r)begin
         first_sdr_data   <= 144'd0;   // **** honey
         read_valid_data_1_r <= 1'b0;
         read_valid_data_1_r1 <= 1'b0;
         read_valid_data_1_r2 <= 1'b0;
      end
      else begin
         read_valid_data_1_r <= read_valid_data_1;
         read_valid_data_1_r1 <= read_valid_data_1_r;
         read_valid_data_1_r2 <= read_valid_data_1_r1;
         if(read_valid_data_1_r1)begin
            first_sdr_data  <= {fifo_80_data_out_r, fifo_70_data_out_r, 
            fifo_60_data_out_r,  fifo_50_data_out_r,  fifo_40_data_out_r, 
            fifo_30_data_out_r,  fifo_20_data_out_r,  fifo_10_data_out_r, fifo_00_data_out_r,   
	    fifo_81_data_out_r,  fifo_71_data_out_r,  fifo_61_data_out_r,  
	    fifo_51_data_out_r,  fifo_41_data_out_r,  fifo_31_data_out_r,  
	    fifo_21_data_out_r,  fifo_11_data_out_r, fifo_01_data_out_r};
            
            
            
            /*
            
            fifo_00_data_out_r, fifo_01_data_out_r, 
            fifo_10_data_out_r,  fifo_11_data_out_r,  fifo_20_data_out_r, 
            fifo_21_data_out_r,  fifo_30_data_out_r,  fifo_31_data_out_r,  
	    fifo_40_data_out_r,  fifo_41_data_out_r,  fifo_50_data_out_r,  
	    fifo_51_data_out_r,  fifo_60_data_out_r,  fifo_61_data_out_r,  
	    fifo_70_data_out_r,  fifo_71_data_out_r,fifo_80_data_out_r,  fifo_81_data_out_r};*/
         end
      end
   end

   // rd address gray counters
   rd_gray_cntr fifo0_rd_addr_inst (.clk(clk90), .reset(reset90_r), .cnt_en(read_valid_data_1), 
                                    .rgc_gcnt(fifo00_rd_addr));

   rd_gray_cntr fifo1_rd_addr_inst (.clk(clk90), .reset(reset90_r), .cnt_en(read_valid_data_1), 
                                    .rgc_gcnt(fifo01_rd_addr));

         
   // 16X1 fifo instantations


   RAM16X1D fifo0_bit0  (.DPO (fifo_00_data_out[0]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[0]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit0  (.DPO (fifo_01_data_out[0]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[0]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));

   RAM16X1D fifo0_bit1  (.DPO (fifo_00_data_out[1]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[1]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit1  (.DPO (fifo_01_data_out[1]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[1]),
                          .DPRA0(fifo01_rd_addr_r[0]), .DPRA1(fifo01_rd_addr_r[1]), 
                          .DPRA2(fifo01_rd_addr_r[2]), .DPRA3(fifo01_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col0_n), .WE(fifo_01_wr_en));

  RAM16X1D fifo0_bit2  (.DPO (fifo_00_data_out[2]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[2]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1), .WE(fifo_00_wr_en));

   RAM16X1D fifo1_bit2  (.DPO (fifo_01_data_out[2]), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]),
                          .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(ddr_dq_in[2]),
                          .DPRA0(fifo00_rd_addr_r[0]), .DPRA1(fifo00_rd_addr_r[1]), 
                          .DPRA2(fifo00_rd_addr_r[2]), .DPRA3(fifo00_rd_addr_r[3]), .SPO(),
                          .WCLK(dqs0_delayed_col1_n), .WE(fifo_01_wr_en));

   RAM16X1D fifo0_bit3  (.DPO (fifo_00_data_out[3]), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]),
                          .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(ddr_dq_in[3]),