📄 data_read_72bit.v
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// Byte5 Fifo instantiation
RAM16X1D fifo0_bit40
( .DPO (fifo_50_data_out[0]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[40]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit40
( .DPO (fifo_51_data_out[0]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[40]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit41
( .DPO (fifo_50_data_out[1]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[41]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit41
( .DPO (fifo_51_data_out[1]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[41]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit42
( .DPO (fifo_50_data_out[2]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[42]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit42
( .DPO (fifo_51_data_out[2]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[42]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit43
( .DPO (fifo_50_data_out[3]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[43]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit43
( .DPO (fifo_51_data_out[3]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[43]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit44
( .DPO (fifo_50_data_out[4]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[44]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit44
( .DPO (fifo_51_data_out[4]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[44]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit45
( .DPO (fifo_50_data_out[5]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[45]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit45
( .DPO (fifo_51_data_out[5]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[45]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit46
( .DPO (fifo_50_data_out[6]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[46]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit46
( .DPO (fifo_51_data_out[6]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[46]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
RAM16X1D fifo0_bit47
( .DPO (fifo_50_data_out[7]),
.SPO( ), .A0 (fifo_50_wr_addr[0]),
.A1 (fifo_50_wr_addr[1]),
.A2 (fifo_50_wr_addr[2]),
.A3 (fifo_50_wr_addr[3]),
.D (ddr_dq_in[47]),
.DPRA0(fifo_50_rd_addr[0]),
.DPRA1(fifo_50_rd_addr[1]),
.DPRA2(fifo_50_rd_addr[2]),
.DPRA3(fifo_50_rd_addr[3]),
.WCLK (dqs5_delayed_col0),
.WE (fifo_50_wr_en)
);
RAM16X1D fifo1_bit47
( .DPO (fifo_51_data_out[7]),
.SPO( ), .A0 (fifo_51_wr_addr[0]),
.A1 (fifo_51_wr_addr[1]),
.A2 (fifo_51_wr_addr[2]),
.A3 (fifo_51_wr_addr[3]),
.D (ddr_dq_in[47]),
.DPRA0(fifo_51_rd_addr[0]),
.DPRA1(fifo_51_rd_addr[1]),
.DPRA2(fifo_51_rd_addr[2]),
.DPRA3(fifo_51_rd_addr[3]),
.WCLK (dqs5_delayed_col0_n),
.WE (fifo_51_wr_en)
);
// Byte6 Fifo instantiation
RAM16X1D fifo0_bit48
( .DPO (fifo_60_data_out[0]),
.SPO( ), .A0 (fifo_60_wr_addr[0]),
.A1 (fifo_60_wr_addr[1]),
.A2 (fifo_60_wr_addr[2]),
.A3 (fifo_60_wr_addr[3]),
.D (ddr_dq_in[48]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK (dqs6_delayed_col0),
.WE (fifo_60_wr_en)
);
RAM16X1D fifo1_bit48
( .DPO (fifo_61_data_out[0]),
.SPO( ), .A0 (fifo_61_wr_addr[0]),
.A1 (fifo_61_wr_addr[1]),
.A2 (fifo_61_wr_addr[2]),
.A3 (fifo_61_wr_addr[3]),
.D (ddr_dq_in[48]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK (dqs6_delayed_col0_n),
.WE (fifo_61_wr_en)
);
RAM16X1D fifo0_bit49
( .DPO (fifo_60_data_out[1]),
.SPO( ), .A0 (fifo_60_wr_addr[0]),
.A1 (fifo_60_wr_addr[1]),
.A2 (fifo_60_wr_addr[2]),
.A3 (fifo_60_wr_addr[3]),
.D (ddr_dq_in[49]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK (dqs6_delayed_col0),
.WE (fifo_60_wr_en)
);
RAM16X1D fifo1_bit49
( .DPO (fifo_61_data_out[1]),
.SPO( ), .A0 (fifo_61_wr_addr[0]),
.A1 (fifo_61_wr_addr[1]),
.A2 (fifo_61_wr_addr[2]),
.A3 (fifo_61_wr_addr[3]),
.D (ddr_dq_in[49]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK (dqs6_delayed_col0_n),
.WE (fifo_61_wr_en)
);
RAM16X1D fifo0_bit50
( .DPO (fifo_60_data_out[2]),
.SPO( ), .A0 (fifo_60_wr_addr[0]),
.A1 (fifo_60_wr_addr[1]),
.A2 (fifo_60_wr_addr[2]),
.A3 (fifo_60_wr_addr[3]),
.D (ddr_dq_in[50]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK (dqs6_delayed_col0),
.WE (fifo_60_wr_en)
);
RAM16X1D fifo1_bit50
( .DPO (fifo_61_data_out[2]),
.SPO( ), .A0 (fifo_61_wr_addr[0]),
.A1 (fifo_61_wr_addr[1]),
.A2 (fifo_61_wr_addr[2]),
.A3 (fifo_61_wr_addr[3]),
.D (ddr_dq_in[50]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK (dqs6_delayed_col0_n),
.WE (fifo_61_wr_en)
);
RAM16X1D fifo0_bit51
( .DPO (fifo_60_data_out[3]),
.SPO( ), .A0 (fifo_60_wr_addr[0]),
.A1 (fifo_60_wr_addr[1]),
.A2 (fifo_60_wr_addr[2]),
.A3 (fifo_60_wr_addr[3]),
.D (ddr_dq_in[51]),
.DPRA0(fifo_60_rd_addr[0]),
.DPRA1(fifo_60_rd_addr[1]),
.DPRA2(fifo_60_rd_addr[2]),
.DPRA3(fifo_60_rd_addr[3]),
.WCLK (dqs6_delayed_col0),
.WE (fifo_60_wr_en)
);
RAM16X1D fifo1_bit51
( .DPO (fifo_61_data_out[3]),
.SPO( ), .A0 (fifo_61_wr_addr[0]),
.A1 (fifo_61_wr_addr[1]),
.A2 (fifo_61_wr_addr[2]),
.A3 (fifo_61_wr_addr[3]),
.D (ddr_dq_in[51]),
.DPRA0(fifo_61_rd_addr[0]),
.DPRA1(fifo_61_rd_addr[1]),
.DPRA2(fifo_61_rd_addr[2]),
.DPRA3(fifo_61_rd_addr[3]),
.WCLK (dqs6_delayed_col0_n),
.WE (fifo_61_wr_en)
);
RAM16X1D fifo0_bit52
( .DPO (fifo_60_data_out[4]),
.SPO( ), .A0 (fifo_60_wr_addr[0]),
.A1 (fifo_60_wr_addr[1]),
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