📄 ddr1_top_72bit.v
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`timescale 1ns/100ps
`include "parameters_72bit.v"
module ddr1_top_72bit (
SYS_CLK,
SYS_CLKb,
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
rst_dqs_div_in,
rst_dqs_div_out,
reset_in,
user_input_data,
user_data_mask,
user_output_data,
user_data_valid,
user_address_cntrl,
user_ba_cntrl,
user_rasb_cntrl,
user_casb_cntrl,
user_web_cntrl,
user_cke_cntrl,
user_csb_cntrl,
user_rst_dqs_div,
user_rst_calib,
user_dqs_reset,
user_dqs_enable,
user_write_enable,
ddr1_dqs,
ddr1_dq,
ddr1_cke,
ddr1_csb,
ddr1_rasb,
ddr1_casb,
ddr1_web,
ddr1_dm,
ddr1_ba,
ddr1_address,
ddr1_clk0,
ddr1_clk0b,
ddr1_clk1,
ddr1_clk1b,
ddr1_clk2,
ddr1_clk2b,
ddr1_clk3,
ddr1_clk3b,
ddr1_clk4,
ddr1_clk4b,
sys_rst_val,
sys_rst90_val,
sys_rst180_val,
sys_rst270_val,
clk_int_val,
clk90_int_val
);
input SYS_CLK;
input SYS_CLKb;
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
input rst_dqs_div_in;
output rst_dqs_div_out;
input reset_in;
input [143:0]user_input_data;
input [17:0]user_data_mask;
output [143:0]user_output_data;
output user_data_valid;
input [12:0]user_address_cntrl;
input [1:0]user_ba_cntrl;
input user_rasb_cntrl;
input user_casb_cntrl;
input user_web_cntrl;
input user_cke_cntrl;
input user_csb_cntrl;
input user_rst_dqs_div;
input user_rst_calib;
input user_dqs_reset;
input user_dqs_enable;
input user_write_enable;
inout [8:0]ddr1_dqs;
inout [71:0]ddr1_dq;
output ddr1_cke;
output ddr1_csb;
output ddr1_rasb;
output ddr1_casb;
output ddr1_web;
output [8:0]ddr1_dm;
output [1:0]ddr1_ba;
output [12:0]ddr1_address;
output ddr1_clk0;
output ddr1_clk0b;
output ddr1_clk1;
output ddr1_clk1b;
output ddr1_clk2;
output ddr1_clk2b;
output ddr1_clk3;
output ddr1_clk3b;
output ddr1_clk4;
output ddr1_clk4b;
output sys_rst_val;
output sys_rst90_val;
output sys_rst180_val;
output sys_rst270_val;
output clk_int_val;
output clk90_int_val;
wire sys_clk_ibuf;
wire [4:0]delay_sel;
wire sys_rst;
wire sys_rst90;
wire sys_rst180;
wire sys_rst270;
wire clk_int;
wire clk90_int;
wire dqs_div_rst;
wire dqs_int_delay_in0;
wire dqs_int_delay_in1;
wire dqs_int_delay_in2;
wire dqs_int_delay_in3;
wire dqs_int_delay_in4;
wire dqs_int_delay_in5;
wire dqs_int_delay_in6;
wire dqs_int_delay_in7;
wire dqs_int_delay_in8;
wire [71:0]dq;
wire write_en_val;
wire reset90_r;
wire [8:0]data_mask_f;
wire [8:0]data_mask_r;
wire [71:0]write_data_falling;
wire [71:0]write_data_rising;
wire clk_int_val2;
wire clk90_int_val2;
assign clk_int_val2 = clk_int;
assign clk90_int_val2 = clk90_int;
assign sys_rst_val = sys_rst;
assign sys_rst90_val = sys_rst90;
assign sys_rst180_val = sys_rst180;
assign sys_rst270_val = sys_rst270;
assign clk_int_val = clk_int;
assign clk90_int_val = clk90_int;
data_path_72bit data_path0 (
.user_data_mask (user_data_mask),
.user_input_data (user_input_data),
.clk (clk_int_val2),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.clk90 (clk90_int_val2),
.reset (sys_rst),
.reset90 (sys_rst90),
.reset180 (sys_rst180),
.reset270 (sys_rst270),
.write_enable (user_write_enable),
.rst_dqs_div_in (dqs_div_rst),
.delay_sel (delay_sel),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.dqs_int_delay_in4 (dqs_int_delay_in4),
.dqs_int_delay_in5 (dqs_int_delay_in5),
.dqs_int_delay_in6 (dqs_int_delay_in6),
.dqs_int_delay_in7 (dqs_int_delay_in7),
.dqs_int_delay_in8 (dqs_int_delay_in8),
.dq (dq),
.u_data_val (user_data_valid),
.user_output_data (user_output_data),
.write_en_val (write_en_val),
.reset90_r_val (reset90_r),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r),
.write_data_falling (write_data_falling),
.write_data_rising (write_data_rising)
);
infrastructure infrastructure0
(
.reset_in (reset_in),
.sys_clk_ibuf (sys_clk_ibuf),
.rst_calib1 (user_rst_calib),
.delay_sel_val1_val(delay_sel),
.sys_rst_val (sys_rst),
.sys_rst90_val (sys_rst90),
.sys_rst180_val (sys_rst180),
.sys_rst270_val (sys_rst270),
.clk_int_val (clk_int),
.clk90_int_val (clk90_int)
);
iobs iobs0
(
.SYS_CLK (SYS_CLK),
.SYS_CLKb (SYS_CLKb),
.clk (clk_int_val2),
.clk90 (clk90_int_val2),
//XST_REMOVECOMMENT .clk180 (clk180),
//XST_REMOVECOMMENT .clk270 (clk270),
.ddr_rasb_cntrl (user_rasb_cntrl),
.ddr_casb_cntrl (user_casb_cntrl),
.ddr_web_cntrl (user_web_cntrl),
.ddr_cke_cntrl (user_cke_cntrl),
.ddr_csb_cntrl (user_csb_cntrl),
.ddr_address_cntrl (user_address_cntrl),
.ddr_ba_cntrl (user_ba_cntrl),
.rst_dqs_div_int (user_rst_dqs_div),
.dqs_reset (user_dqs_reset),
.dqs_enable (user_dqs_enable),
.ddr_dqs (ddr1_dqs),
.ddr_dq (ddr1_dq),
.write_data_falling(write_data_falling),
.write_data_rising (write_data_rising),
.write_en_val (write_en_val),
.reset90_r (reset90_r),
.data_mask_f (data_mask_f),
.data_mask_r (data_mask_r),
.sys_clk_ibuf (sys_clk_ibuf),
.ddr1_clk0 (ddr1_clk0),
.ddr1_clk0b (ddr1_clk0b),
.ddr1_clk1 (ddr1_clk1),
.ddr1_clk1b (ddr1_clk1b),
.ddr1_clk2 (ddr1_clk2),
.ddr1_clk2b (ddr1_clk2b),
.ddr1_clk3 (ddr1_clk3),
.ddr1_clk3b (ddr1_clk3b),
.ddr1_clk4 (ddr1_clk4),
.ddr1_clk4b (ddr1_clk4b),
.ddr_rasb (ddr1_rasb),
.ddr_casb (ddr1_casb),
.ddr_web (ddr1_web),
.ddr_ba (ddr1_ba),
.ddr_address (ddr1_address),
.ddr_cke (ddr1_cke),
.ddr_csb (ddr1_csb),
.rst_dqs_div (dqs_div_rst),
.rst_dqs_div_in (rst_dqs_div_in),
.rst_dqs_div_out ( rst_dqs_div_out),
.dqs_int_delay_in0 (dqs_int_delay_in0),
.dqs_int_delay_in1 (dqs_int_delay_in1),
.dqs_int_delay_in2 (dqs_int_delay_in2),
.dqs_int_delay_in3 (dqs_int_delay_in3),
.dqs_int_delay_in4 (dqs_int_delay_in4),
.dqs_int_delay_in5 (dqs_int_delay_in5),
.dqs_int_delay_in6 (dqs_int_delay_in6),
.dqs_int_delay_in7 (dqs_int_delay_in7),
.dqs_int_delay_in8 (dqs_int_delay_in8),
.dq (dq),
.ddr_dm (ddr1_dm)
);
endmodule
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